研究生: |
羅勻辰 Yun-Chen Law |
---|---|
論文名稱: |
應用於耳機的含D類放大器之改良強健式三角積分數位/類比轉換器 A D/A Converter Composed of a Hybrid-Sturdy MASH-21 Modulator and a Class-D Amplifier for Earphones |
指導教授: |
姚嘉瑜
Chia-Yu Yao |
口試委員: |
陳筱青
Hsiao-Chin Chen 彭盛裕 Sheng-Yu Peng |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2020 |
畢業學年度: | 108 |
語文別: | 中文 |
論文頁數: | 100 |
中文關鍵詞: | 內插濾波器 、三角積分調變器 、Sturdy-MASH 、雜訊移頻 、D類功率放大器 |
外文關鍵詞: | Interpolation filter, delta-sigma modulator, Sturdy-MASH, noise shaping, class D power amplifier |
相關次數: | 點閱:235 下載:0 |
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隨著多媒體產業的蓬勃發展,對於音樂品質的要求也越來越高,因此,應用於音頻之數位/類比轉換器所扮演的角色也越來越重要。如何同時達到消費性電子產品的低成本需求、專業錄音用途所引頸期盼的高解析度、以及可攜式產品要求的低功率消耗,將會是極富挑戰的研究課題。因此,本篇設計一應用於CD音樂規格之三角積分調變數位/類比轉換器,由改良強建式三角積分調變器以及應用於音頻之D類功率放大器組成。
其中,本篇論文設計的差動D類功率放大器會輸出三個電壓準位,來降低訊號轉態時的平均輸出電壓擺幅,並且為了降低諧波失真,採用全橋式架構(H bridge)的D類功率放大器,雖然相較於半橋式,面積會增加,但是全橋式可以消除偶次倍頻,並且可以做電流三個準位的還原(正向、反向、不流),此外,在尺寸的部分搭配主動濾波器做調整,可以降低功耗與面積並且提高訊號的還原度。
而要控制D類功率放大器能輸出三個準位的電壓,就需要兩位元的控制器來達成,於是我們選用三階的改良強建式三角積分調變器(Hybrid-SMASH2-1)做為控制D類放大器的控制器,改良強建式三角積分調變器改良自Sturdy-Mash(SMASH)的架構,能比SMASH多消除第一級量化雜訊,並調變出1.5位元的數位訊號去驅動D類功率放大器,藉此增加訊號解析度。
本篇論文晶片使用TSMC 0.18 um製程,操作電壓為1.8V,取樣頻率2.8224 MHz,OSR為64,系統頻寬22.05kHz,實際量測數位部分輸出SNDR為96.7dB,類比輸出則為SNDR為34dB,晶片面積包含pad為1.63mm^2,功率消耗為3.35 mW,效率為98.5%。
With the rapid development of the multimedia industry, the requirement of audio quality becomes higher. Therefore, audio digital/analog converters play an increasingly essential role in our lives. How to simultaneously meet the low-cost requirements of consumer electronics products, the high resolution expected by professional recording applications, and the low power consumption required by portable products will be extremely challenging topics. Hence, this paper presents a D/A converter (DAC) composed of a novel hybrid sturdy-MASH-21 (HSMASH-21) delta-sigma modulator (DSM) and a class-D amplifier for audio applications.
This work employs a class-D amplifier with three level outputs at VDD, VDD/2, and GND to decrease the average voltage swing in output transitions and, thus, to reduce the output harmonic amplitudes. Therefore, the class D audio amplifier employs an improved H bridge circuit. Although the area of the H-bridge architecture will be larger than the half-bridge architecture, the H-bridge architecture can eliminate even harmonics. In addition, active filters are used to filter out the output signal. It can reduce power consumption and chip area, and improve signal restoration.
To properly control the connection of the amplifier output to three discrete levels, we need a two-bit control signal. Hence, a three-stage Hybrid-SMASH delta-sigma modulator (DSM) is suitable to serve as the controller. Hybrid-SMASH structure is modified from the architecture of SMASH. It can eliminate the quantization noise from its first stage. The 1.5-bit digital signal is modulated to drive the class D power amplifier, thereby improving the signal resolution.
The chip is designed using TSMC 0.18-μm CMOS technology. The sampling rate is 2.8224M Hz and the over-sampling ratio is 64. The supply voltage is 1.8V and bandwidth is 22.05k Hz. The SNDR of the digital and analog parts of the chip output pad are 96.7 dB and 34 dB, respectively. The chip area including the pad is 1.63 mm2. The estimated power consumption of the chip is 3.35 mW and power efficiency is 98.5%.
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