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研究生: 羅勻辰
Yun-Chen Law
論文名稱: 應用於耳機的含D類放大器之改良強健式三角積分數位/類比轉換器
A D/A Converter Composed of a Hybrid-Sturdy MASH-21 Modulator and a Class-D Amplifier for Earphones
指導教授: 姚嘉瑜
Chia-Yu Yao
口試委員: 陳筱青
Hsiao-Chin Chen
彭盛裕
Sheng-Yu Peng
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 中文
論文頁數: 100
中文關鍵詞: 內插濾波器三角積分調變器Sturdy-MASH雜訊移頻D類功率放大器
外文關鍵詞: Interpolation filter, delta-sigma modulator, Sturdy-MASH, noise shaping, class D power amplifier
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  • 隨著多媒體產業的蓬勃發展,對於音樂品質的要求也越來越高,因此,應用於音頻之數位/類比轉換器所扮演的角色也越來越重要。如何同時達到消費性電子產品的低成本需求、專業錄音用途所引頸期盼的高解析度、以及可攜式產品要求的低功率消耗,將會是極富挑戰的研究課題。因此,本篇設計一應用於CD音樂規格之三角積分調變數位/類比轉換器,由改良強建式三角積分調變器以及應用於音頻之D類功率放大器組成。

    其中,本篇論文設計的差動D類功率放大器會輸出三個電壓準位,來降低訊號轉態時的平均輸出電壓擺幅,並且為了降低諧波失真,採用全橋式架構(H bridge)的D類功率放大器,雖然相較於半橋式,面積會增加,但是全橋式可以消除偶次倍頻,並且可以做電流三個準位的還原(正向、反向、不流),此外,在尺寸的部分搭配主動濾波器做調整,可以降低功耗與面積並且提高訊號的還原度。

    而要控制D類功率放大器能輸出三個準位的電壓,就需要兩位元的控制器來達成,於是我們選用三階的改良強建式三角積分調變器(Hybrid-SMASH2-1)做為控制D類放大器的控制器,改良強建式三角積分調變器改良自Sturdy-Mash(SMASH)的架構,能比SMASH多消除第一級量化雜訊,並調變出1.5位元的數位訊號去驅動D類功率放大器,藉此增加訊號解析度。

    本篇論文晶片使用TSMC 0.18 um製程,操作電壓為1.8V,取樣頻率2.8224 MHz,OSR為64,系統頻寬22.05kHz,實際量測數位部分輸出SNDR為96.7dB,類比輸出則為SNDR為34dB,晶片面積包含pad為1.63mm^2,功率消耗為3.35 mW,效率為98.5%。


    With the rapid development of the multimedia industry, the requirement of audio quality becomes higher. Therefore, audio digital/analog converters play an increasingly essential role in our lives. How to simultaneously meet the low-cost requirements of consumer electronics products, the high resolution expected by professional recording applications, and the low power consumption required by portable products will be extremely challenging topics. Hence, this paper presents a D/A converter (DAC) composed of a novel hybrid sturdy-MASH-21 (HSMASH-21) delta-sigma modulator (DSM) and a class-D amplifier for audio applications.

    This work employs a class-D amplifier with three level outputs at VDD, VDD/2, and GND to decrease the average voltage swing in output transitions and, thus, to reduce the output harmonic amplitudes. Therefore, the class D audio amplifier employs an improved H bridge circuit. Although the area of the H-bridge architecture will be larger than the half-bridge architecture, the H-bridge architecture can eliminate even harmonics. In addition, active filters are used to filter out the output signal. It can reduce power consumption and chip area, and improve signal restoration.

    To properly control the connection of the amplifier output to three discrete levels, we need a two-bit control signal. Hence, a three-stage Hybrid-SMASH delta-sigma modulator (DSM) is suitable to serve as the controller. Hybrid-SMASH structure is modified from the architecture of SMASH. It can eliminate the quantization noise from its first stage. The 1.5-bit digital signal is modulated to drive the class D power amplifier, thereby improving the signal resolution.

    The chip is designed using TSMC 0.18-μm CMOS technology. The sampling rate is 2.8224M Hz and the over-sampling ratio is 64. The supply voltage is 1.8V and bandwidth is 22.05k Hz. The SNDR of the digital and analog parts of the chip output pad are 96.7 dB and 34 dB, respectively. The chip area including the pad is 1.63 mm2. The estimated power consumption of the chip is 3.35 mW and power efficiency is 98.5%.

    目錄 致謝 i 摘要 ii Abstract iv 目錄 vi 圖目錄 ix 表目錄 xiii 第一章 概論 1 1.1前言 1 1.2研究動機 1 第二章 超取樣三角積分調變器 3 2.1簡介 3 2.2 奈奎斯特取樣定理 3 2.3量化誤差 4 2.4超取樣技術 7 2.5三角積分調變[1] 8 2.6 一階三角積分調變器[1] 11 2.7二階與多階三角積分調變器[1] 12 2.7.1 二階三角積分調變器 12 2.7.2 多階三角積分調變器[1] 15 2.8三角積分調變器架構介紹[1] 16 2.8.1單迴路架構 (single-loop) 16 2.8.2 多級串疊MASH (Multi-stAge noise SHaping)[1] 17 2.8.3 SMASH (Sturdy-MASH ) 19 2.8.4強健式HSMASH (Hybrid- SMASH) 21 第三章 D類功率放大器 23 3.1 功率放大器簡介[9] 23 3.2 線性功率放大器[10] 24 3.2.1 A類功率放大器 24 3.2.2 B類功率放大器[9] 26 3.2.3 AB類功率放大器[9] 28 3.3 D類功率放大器 30 3.3.1 D類功率放大器工作原理[9] 30 3.3.2 脈衝寬度調變 31 3.3.3 三角積分調變 32 第四章 系統與電路架構 33 4.1系統設計 33 4.2內插濾波器 (Interpolation Filter) 34 4.2.1內插濾波器電路設計 34 4.2.2 內插濾波器模擬結果 38 4.3 HSMASH-21 三角積分調變器實現 40 4.3.1 HSMASH-21電路設計 41 4.3.2 HSMASH-21模擬結果 46 4.4 D類功率放大器 49 4.4.1 控制D類功率放大器開關的邏輯閘電路 49 4.4.2 非重疊電路(non-overlap circuit) 50 4.4.3 緩衝器 53 4.4.4 輸出級電路—D類功率放大器 54 4.4.5 輸出級電路—主動式低通濾波器 55 4.5晶片佈局 58 4.6電路模擬 59 4.6.1 前模擬結果 59 4.6.2 後模擬結果 64 第五章 量測結果 69 5.1量測環境設定 69 5.2 穩壓電路 69 5.3 量測結果 71 5.4 效能比較表 80 第六章 結論與展望 82 6.1結論 82 6.2 未來展望 82 參考文獻 84

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