應用資料加權平均技術之低電壓連續時間三角積分調變器晶片設計

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研究生：	賴彥誠 Yan-cheng Lai
論文名稱：	應用資料加權平均技術之低電壓連續時間三角積分調變器晶片設計 A Low-Voltage Continuous-Time Sigma-Delta Modulator Chip Design with DWA Technology
指導教授：	黃進芳 Jhin-fang Huang 劉榮宜 Ron-yi Liu
口試委員:	徐敬文 Ching-wen Hsue 張勝良 Sheng-lyang Jang 陳國龍 Kuo-lung Chen
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	114
中文關鍵詞：	資料加權平均、三角積分調變器、連續時間
外文關鍵詞：	data weighted averaging, sigma-delta modulator, continuous-time
相關次數：	點閱：240 下載：2
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近年來，在無線應用方面，連續時間式三角積分調變器的發展逐漸受到關注，因其與離散時間三角積分調變器相比具有較低的功率消耗和較寬的輸入頻寬。三角積分調變技術已廣泛使用在寬頻及高精確度的類比/混合訊號積體電路應用中，例如類比數位資料轉換器、數位類比資料轉換器、頻率合成器和功率放大器。
在考量低電壓設計的情況下，交換電容電路中的高阻抗開關會限制訊號的大小和取樣頻率。由於積分器頻寬的限制，很難達到寬頻具有高解析度，因此利用連續時間三角積分調變器可以解決這些問題。對於一個多位元三角積分調變器而言，整個系統的性能直接取決於回授路徑中的多位元數位類比轉換器(DAC)的線性度。為了改善數位類比轉換器的非線性特性，各種不同的動態元件匹配(DEM)技術已被提出。在此調變器中，使用了資料加權平均演算法並且對於數位類比轉換器的元件不匹配提供一階雜訊移頻的效果。另一方面，由製程變易所造成迴路係數偏移的影響，藉由使用電容調整電路來克服此問題。在數位訊號處理方面，探討降頻濾波器的設計與分析，包含了梳型濾波器和有限脈衝響應濾波器。
本論文的研究方向為設計並實現應用於寬頻的連續時間低電壓三角積分調變器，此三角積分調變器主要包含主動式電阻電容電路、資料權重平均電路、回授DAC電路跟操作頻率在160MHz的多位元量化器來實現。應用台積電0.18微米1P6M的標準製程來實現晶片設計，在1.2伏特的供應電源下，功耗僅19.8mW。量測結果顯示在取樣頻率160MHz，超取樣比為8之下，訊號頻寬在10MHz內，其最大的訊號雜訊比與訊號雜訊失真比分別為51dB與48dB，其動態範圍為54dB。

Recently, continuous-time (CT) ΣΔ modulators gain growing interest in wireless applications for their lower consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts. Sigma-delta modulation techniques have been widely used in broadband and high accuracy analog/mixed-signal IC applications, such as analog-to-digital data converters (ADCs), digital-to-analog data converters (DACs), frequency synthesis, and power amplification.
In the situation of low-voltage design, the signal dynamic range and sampling frequency are restricted by the high switch resistance in the switched-capacitor (SC) circuits. Due to the bandwidth limitation of the integrators, it is difficult to achieve wideband with high resolution. Hence, continuous-time ΣΔ modulator can be used to solve these problems. For a multibit ΣΔ modulator, the performance is directly related to the linearity of the internal multibit DAC in the feedback path. Various dynamic element matching (DEM) techniques have been proposed to improve the nonlinearity of the internal DAC. In the modulator, the data weighted averaging (DWA) algorithm is employed and provide first-order noise shaping of the DAC element mismatches. On the other hand, Capacitor tuning circuit is utilized to overcome loop coefficient shifts due to process variations. In digital signal processing, the design and analysis of the decimation filter is discussed including the comb filter and the finite impulse response (FIR) filter.
In this thesis, we design and implement a low voltage, continuous-time sigma delta modulator for broadband application. The modulator mainly contains active-RC integrator, DWA circuit, feedback DAC circuit, and 4-bits quantizer operation at 160MHz. The modulator dissipates 19.8 mW at 1.2 V supply voltage and is fabricated in the TSMC 0.18 um 1P6M CMOS technology. Measurement results show the modulator achieves 51 dB SNR, a peak 48 dB SNDR and 54dB dynamic range over a 10 MHz band at an over-sampling ratio of 8.

Acknowledgements                                           I
Abstract (in Chinese)                                      III
Abstract (in English)                                      V
Table of Contents                                        VII
List of Figures                                            IX
List of Tables                                            XI

Chapter 1 Introduction
1	Motivation                                                1
2	Organization                                               3
Chapter 2 Fundamentals of Sigma-Delta Modulators
1	Introduction                                               4
2	Analog-to-Digital Converters                                 4
3	Quantization                                              5
4	Oversampling                                             8
5	Noise-Shaping ΔΣ Modulator                                 9
6	Multi-Bit ΔΣ Modulator                                     11
7	Dynamic Element Matching                                 11
8	Continuous-Time and Discrete-Time Loop Filter                 12
9	Performance Metrics                                       13
10	Paper Survey                                             15
11	Summary                                                17
Chapter 3 Design of Continuous-Time Sigma-Delta Modulators
1	Introduction                                              18
2	System Architecture                                        18
3	DT-to-CT conversion of Sigma-Delta Modulator                 19
3.1		Modified Z-Transform                                 23
3.2		Excess Loop Delay in Continuous-Time ΣΔ modulator        27
4	Analysis of Non-Ideal Effects                                28
4.1		Integrator Nonlinearity                                 29
4.2		Finite Op Amp Gain                                   30
4.3		Jitter Effects in CT ΣΔ modulator                         32
4.4		Time-Constant Error                                   34
5	Summary                                                36
Chapter 4 Circuit Implementation
1	Resistor-Capacitor Integrators                                38
2	Comparator                                               42
3	Four-bit Quantizer                                         44
4	Feedback DACs                                           45
5	DWA circuit                                              47
6	Clock Generator                                           48
7	Time Constant Tuning                                      49
8	Floorplain and layout                                      50
9	Simulation Results                                         51
10	Summary                                                53
Chapter 5 Decimation Filter Design
1	Introduction                                              54
2	Digital Filter Design                                       54
2.1		Comb Filter                                         55
2.2		FIR Filter                                            57
3	Decimation Filter Architecture and Design                      60
3.1		Single-Stage Decimation Filter                           60
3.2		Multistage Decimation Filter                            62
4	Simulation Results                                         72
5	Summary                                                73
Chapter 6 Test Setup and Experimental Result
1	Test Setup                                                76
2	Experimental Results                                       77
3	Performance Comparison                                    82
4	Summary                                                84
Chapter 7 Conclusions
1	Conclusions                                              85
2	Future Work                                              85
Bibliography                                             87
Appendix                                                   92

                                

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