研究生: |
劉育勳 Yu-Hsun - Liu |
---|---|
論文名稱: |
低功耗等效13.5位元之改良強健式MASH-21三角積分類比數位轉換器 A Low-Power 13.5-bit Modified Sturdy MASH-21 Delta-Sigma AD Converter |
指導教授: |
姚嘉瑜
Chia-Yu Yao |
口試委員: |
陳筱青
none 彭盛裕 Sheng-Yu |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2017 |
畢業學年度: | 105 |
語文別: | 中文 |
論文頁數: | 88 |
中文關鍵詞: | 三角積分調變器 、Sturdy-MASH 、電容積分器 、多級雜訊移頻 |
外文關鍵詞: | Delta-sigma Modulator, Sturdy-MASH, Switch-Capacitor Integrator, Multi-Stage noise Shaping. |
相關次數: | 點閱:350 下載:2 |
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語音及生醫檢測系統的應用上,低功耗資料轉換器扮演著重要的角色,負責將類比訊號轉換成為數位訊號以提供後端的微處理器做進一步的分析與處理。類比數位轉換器有多種架構,而其中之一的三角積分調變器與超取樣技術具有低複雜度且可達到中至高解析度,三角積分調變器最大的特色便是將量化雜訊移頻至高頻,並使用低通濾波器濾除雜訊,達到高解析度的數位訊號。
本篇論文設計一個應用在語音或生醫應用之低功耗與低電壓的三角積分類比數位轉換器,系統將Sturdy-MASH加以改進,稱之為Modified Sturdy MASH,並以反相器取代電容積分器中的傳統運算放大器,實現一個2-1架構之低功耗雜訊移頻的三角積分調變器,晶片使用UMC 0.18um製程,晶片面積0.742mm^2,操作電壓1V,取樣頻率1.28MHz,系統頻寬10kHz,解析度達到13.5bit,功率消耗為61uW。
關鍵字:三角積分調變器、Sturdy-MASH、電容積分器、多級雜訊移頻
Low-power analog-to-digital converter (ADC) plays an important role in speech and biomedical applications. It provides converted digital signal to the back-end microprocessor for further processing.
There are many types of ADCs, one is the Delta-Sigma modulator which has a unique characteristic of shaping the quantization noise to high frequencies and conserves the desired signal in the low frequencies. The quantization noise can be removed by a low-pass filter easily. This advantage makes the Delta-Sigma modulator achieve high resolution.
This thesis presents a low-power modified sturdy-MASH-21 delta-sigma AD converter with 13.5-bit resolution. We modified the sturdy-MASH architecture by employing inverting integrators as well as the non-inverting integrator. We use inverters to replace conventional OP Amplifiers in the switch-capacitor integrator. The designed chip was fabricated in UMC 0.18um CMOS process. The chip area is 0.742mm^2. The operating voltage is set at 1 volt. The sampling frequency is set at 1.28 MHz and the system bandwidth is set to 10 kHz. Hence the over-sampling ratio is 64. The power consumption of the proposed ADC is 61uW.
Keyword: Delta-sigma Modulator, Sturdy-MASH, Switch-Capacitor Integrator, Multi-Stage noise Shaping.
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