研究生: |
林后軒 Hou-Hsuan Lin |
---|---|
論文名稱: |
音頻應用離散型三角積分類比數位轉換器之設計與實現 Design and Implementation of Discrete-Time Delta-Sigma ADC for Audio Applications |
指導教授: |
鍾勇輝
Yung-Hui Chung |
口試委員: |
陳信樹
Hsin-Shu Chen 陳筱青 Hsiao-Chin Chen 陳伯奇 Poki Chen |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2023 |
畢業學年度: | 111 |
語文別: | 中文 |
論文頁數: | 79 |
外文關鍵詞: | Delta-Sigma modulation, discrete time, CIFB |
相關次數: | 點閱:154 下載:0 |
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本論文為探討離散型三角積分調變器(Discrete-Time Delta-Sigma Modulator, DT-DSM)的設計與實踐。由於DT-DSM具有過取樣(Oversampling)和雜訊整形 (Noise-shaping)的特性,因此在架構實踐上能夠達到較高的解析度。故在目標頻帶為音頻的高解析度ADC實踐上,十分適合使用DT-DSM架構。
在聯電180奈米製程下,我設計了一個DSM晶片。這顆晶片是選用含有前饋路徑的Cascade Of Integrators With Feedback(CIFB)架構。藉由添加前饋路徑,能夠降低積分器的輸出擺幅,進而降低跨導放大器(Operational Transconductance Amplifiers, OTA)所需的規格。此晶片使用了以反相器為基底的電流再利用跨導放大器(Current Reuse Inverter-based OTA)架構。藉由其輸入跨導較大的特點,能夠在節省功耗的同時,滿足積分器穩定時間(Settling Time)的需求。最後藉由將加法器及量化器結合至一個四位元的連續漸進式類比數位轉換電路(SAR ADC),可以降低功耗並提高量化器的解析度。在OSR為64且取樣頻率為3.2MHz的情況下,功耗為0.85毫瓦。在輸入大小為-0.6dBFS時,量測到的訊號對雜訊失真比(SNDR)為89.3 dB、無雜散動態範圍(SFDR)則為102.5 dB,其動態範圍(Dynamic Range, DR)則為89.8 dB。這個DT-DSM的Schreier FOM為164 dB。
This thesis proposes the design and implementation of a discrete-time delta-sigma-modulator (DT-DSM). Because of its characteristics of oversampling and noise-shaping, it can achieve higher resolution. Therefore, in the implementation of high-resolution ADCs for audio applications, it is very suitable to use the DT-DSM structure.
In this work, I designed a DT-DSM chip in UMC 180nm CMOS technology. The architecture of the chip is a cascade of integrators with feedback (CIFB) architecture with multiple feedforward paths. By adding these feedforward paths, the output swing of integrators can be reduced, thereby reducing the required specifications of the operational transconductance amplifiers (OTAs). A current-reuse inverter-based OTA architecture is used in this chip. Due to its large input transconductance, it can meet the integrator’s settling time requirements while saving power consumption. Finally, by combining the adder and quantizer into a 4-bit successive-approximation register (SAR) ADC, the power consumption can be reduced and the resolution of the quantizer can be improved. With an OSR of 64 and 3.2 MHz sampling frequency, the power consumption is 0.85 mW. With a -0.6dBFS input amplitude, the measured signal-to-noise-distortion ratio (SNDR) is 89.3 dB, the spurious-free dynamic range (SFDR) is 102.5 dB, and the dynamic range (DR) is 89.8 dB. This DT-DSM achieves a Schreier FOM of 164 dB.
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