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研究生: 林后軒
Hou-Hsuan Lin
論文名稱: 音頻應用離散型三角積分類比數位轉換器之設計與實現
Design and Implementation of Discrete-Time Delta-Sigma ADC for Audio Applications
指導教授: 鍾勇輝
Yung-Hui Chung
口試委員: 陳信樹
Hsin-Shu Chen
陳筱青
Hsiao-Chin Chen
陳伯奇
Poki Chen
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2023
畢業學年度: 111
語文別: 中文
論文頁數: 79
外文關鍵詞: Delta-Sigma modulation, discrete time, CIFB
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  • 本論文為探討離散型三角積分調變器(Discrete-Time Delta-Sigma Modulator, DT-DSM)的設計與實踐。由於DT-DSM具有過取樣(Oversampling)和雜訊整形 (Noise-shaping)的特性,因此在架構實踐上能夠達到較高的解析度。故在目標頻帶為音頻的高解析度ADC實踐上,十分適合使用DT-DSM架構。
    在聯電180奈米製程下,我設計了一個DSM晶片。這顆晶片是選用含有前饋路徑的Cascade Of Integrators With Feedback(CIFB)架構。藉由添加前饋路徑,能夠降低積分器的輸出擺幅,進而降低跨導放大器(Operational Transconductance Amplifiers, OTA)所需的規格。此晶片使用了以反相器為基底的電流再利用跨導放大器(Current Reuse Inverter-based OTA)架構。藉由其輸入跨導較大的特點,能夠在節省功耗的同時,滿足積分器穩定時間(Settling Time)的需求。最後藉由將加法器及量化器結合至一個四位元的連續漸進式類比數位轉換電路(SAR ADC),可以降低功耗並提高量化器的解析度。在OSR為64且取樣頻率為3.2MHz的情況下,功耗為0.85毫瓦。在輸入大小為-0.6dBFS時,量測到的訊號對雜訊失真比(SNDR)為89.3 dB、無雜散動態範圍(SFDR)則為102.5 dB,其動態範圍(Dynamic Range, DR)則為89.8 dB。這個DT-DSM的Schreier FOM為164 dB。


    This thesis proposes the design and implementation of a discrete-time delta-sigma-modulator (DT-DSM). Because of its characteristics of oversampling and noise-shaping, it can achieve higher resolution. Therefore, in the implementation of high-resolution ADCs for audio applications, it is very suitable to use the DT-DSM structure.
    In this work, I designed a DT-DSM chip in UMC 180nm CMOS technology. The architecture of the chip is a cascade of integrators with feedback (CIFB) architecture with multiple feedforward paths. By adding these feedforward paths, the output swing of integrators can be reduced, thereby reducing the required specifications of the operational transconductance amplifiers (OTAs). A current-reuse inverter-based OTA architecture is used in this chip. Due to its large input transconductance, it can meet the integrator’s settling time requirements while saving power consumption. Finally, by combining the adder and quantizer into a 4-bit successive-approximation register (SAR) ADC, the power consumption can be reduced and the resolution of the quantizer can be improved. With an OSR of 64 and 3.2 MHz sampling frequency, the power consumption is 0.85 mW. With a -0.6dBFS input amplitude, the measured signal-to-noise-distortion ratio (SNDR) is 89.3 dB, the spurious-free dynamic range (SFDR) is 102.5 dB, and the dynamic range (DR) is 89.8 dB. This DT-DSM achieves a Schreier FOM of 164 dB.

    論文摘要 Abstract 致謝 目錄 表格目錄 圖目錄 第一章 序論 1-1. 研究動機與目的 1-2. 章節說明 第二章 三角積分調變器技術 2-1. 奈奎斯特理論 2-2. 過取樣理論與雜訊整形的技術 2-3. 積分器的非理想效應 2-3-1 轉移函數的偏移 2-3-2 迴轉率與單位增益頻寬的選擇 第三章 三角積分調變器的架構與係數的選擇 3-1. 三角積分調變器(DSM) 3-1-1. 回授型串接積分器(CIFB) 3-1-2. 前饋型串接積分器(CIFF) 3-2. 係數選擇流程圖 3-3. 回授電容的非線性與數位校正技術 第四章 二階CIFB之晶片實踐 4-1. MATLAB的分析 4-1-1 晶片係數選擇 4-1-2 雜訊轉移函數的零點偏移 4-1-3 係數偏移 4-1-4 雜訊分析 4-1-5 電路實踐和MATLAB模擬 4-2. 取樣電路 4-3. 交換電容式積分器 4-3-1 反相器為基底的跨導放大器(Inverter-based OTA) 4-3-2 共模回授電路 4-3-3 斬波技術的控制電路 4-4. 結合前饋路徑的量化器 4-5. 資料權重平均控制電路 4-5-1 二進制轉溫度計碼電路 4-5-2 數位積分器 4-5-3 輪轉偏移電路 4-6. 電路佈局 4-7. 模擬結果 4-8. 量測結果 第五章 結論與未來展望 5-1. 結論 5-2. 未來展望 參考文獻

    [1] R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters Piscataway, NJ, USA: Wiley, 2005.
    [2] R. Schreier, J. Silva, J. Steensgaard and G. C. Temes, "Design-oriented estimation of thermal noise in switched-capacitor circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2358-2368, Nov. 2005.
    [3] Y.-H. Chung, C.-W. Yen, and C.-H. Tsai, "A 12-bit 1-MS/s 26-μW SAR ADC for Sensor Applications," Physical Sciences Reviews, vol. 3, no. 1, 2018, pp.1-15. DOI:10.1515/psr-2016-0014.
    [4] X. Fu, K. El-Sankary, and Y. Yin, ‘‘A High-Performance OTA with Hybrid of Inverter-Based OTA and Nauta OTA for High Speed Applications,’’ in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2021, pp. 1–5.
    [5] O. Choksi and L. R. Carley, “Analysis of switched-capacitor common-mode feedback circuit,” IEEE Trans. Circuits and Systems. II: Analog and Digital Signal Processing, vol. 50, no. 12, pp. 906–917, Dec. 2003.
    [6] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of Op-Amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, pp. 1584–1614, Nov. 1996.
    [7] B. Zhang, R. Dou, L. Liu and N. Wu, "A 91.2dB SNDR 66.2fJ/conv. dynamic amplifier based 24kHz ΔΣ modulator," 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 317- 320, Toyama, Japan, 2016.
    [8] L. Liu, D. Li, Y. Ye, L. Chen and Z. Wang, "A 95dB SNDR Audio ΔΣ modulator in 65nm CMOS," 2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, pp. 1-4.
    [9] X. Tang, B. Kasap, L. Shen, X. Yang, W. Shi and N. Sun, "An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier," 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019, pp. C140-C141.
    [10] S. Ma et al., “A discrete-time audio delta-sigma modulator using dynamic amplifier with speed enhancement and flicker noise reduction techniques,” IEEE J. Solid-State Circuits, vol. 55, no. 2, pp. 333–343, Feb. 2020.
    [11] M. Grassi et al., “A multi-mode SC audio sigma-delta modulator for MEMS microphones with reconfigurable power consumption, noise-shaping order, and DR,” in Proc. 42nd Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2016, pp. 245–248.
    [12] M. Honarparvar et al., “A 0.9V 100 μW feedforward adder-less inverter-based mash delta-sigma modulator with 91 dB dynamic range and 20 kHz bandwidth,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 11, pp. 3675–3687, Nov. 2018.

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