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研究生： 王禮銘
Li-Ming Wang
論文名稱： 應用於LTE之串接式雙迴路頻率合成器
A Cascaded Dual-Loop Frequency Synthesizer for Long Term Evolution Application
指導教授： 陳筱青
Hsiao-Chin Chen
口試委員: 陳雅淑
Ya-Shu Chen
邱弘緯
Hung-Wei Chiu
汪濤
Wang Tao
學位類別： 碩士
Master
系所名稱： 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 中文
論文頁數： 107
中文關鍵詞： 雙迴路頻率合成器 、三角積分調變分數型頻率合成器 、注入鎖定式倍頻器 、長期演進技術
外文關鍵詞： Dual-Loop Frequency Synthesizer, Delta-Sigma Modulation Fractional-N Synthesizer, Injection-Locked Frequency Multiplier, Long Term Evolution
相關次數： 點閱：293  下載：11 
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    • 本論文研究出一個符合LTE頻段標準的串接式雙迴路三角積分調變分數型頻率合成器，由文獻可知日本、韓國、歐洲、美國與中國所包含的頻率範圍從788 MHz到862 MHz與1.9 GHz到2.6 GHz，此分數型頻率合成器可產生出上述頻率範圍的六倍頻或兩倍頻(3.8 GHz~5.2 GHz)。

    本論文的串接式雙迴路三角積分調變分數型頻率合成器使用台積電0.18 μm CMOS製程實現，操作電壓在1.8 V與1.2 V，晶片面積為1.736 mm2，功率消耗71.51 mW。第一級迴路使用可產生石英震盪器八倍頻率的注入鎖定式倍頻器當作第二級迴路的參考訊號，以此降低第二級迴路除數，進而使得迴路頻寬內的相位雜訊可以有效降低，並且將三角積分調變器的量化雜訊對系統的相位雜訊影響降到最小，量測結果在迴路頻寬內的輸出相位雜訊可以降低約-90 dBc/Hz@100 kHz，迴路頻寬外則為-1107.0 dBc/Hz@7.5 MHz。

    This thesis is researching a cascaded dual-loop delta-sigma modulation fractional-N frequency synthesizer for long term evolution applications. From the literature, we can know that the long term evolution’s frequency ranges of Japan, Europe, United State and China which are covering from 788 MHz to 862 MHz and 1.9 GHz to 2.6 GHz, so we designed the output frequency ranges of this fractional-N frequency synthesizer are six times or two times of the above frequencies (3.8 GHz ~ 5.2 GHz).

    This cascaded dual-loop fractional-N frequency synthesizer is design in the TSMC 0.18μm CMOS process, the supply voltage is 1.8 V and 1.2 V, chip area is 1.736 mm2 and the total power consumption is 71.51 mW. The synthesizer’s first loop is produced by the injection-locked frequency multiplier which can produce 8 times frequency of crystal oscillator, by using first loop’s high output frequency as second loop’s reference frequency, the second loop’s divide ratio can be reduced then the output in-band phase noise of this synthesizer can be reduced to -90 dBc/Hz@100 kHz, out-of-band phase noise is -117.0 dBc/Hz@7.5 MHz, also due to high reference, quantization noise of delta-sigma modulation can be pushed to much higher frequency, thus output phase noise will not be impacted by quantization noise more.

    摘要………………………………………………i Abstract…………………………………………iii 致謝………………………………………………v 目錄………………………………………………vii 圖目錄……………………………………………xi 表目錄……………………………………………xvii 第一章 緒論……………………………………1 1.1 簡介………………………………………1 1.2 章節簡介…………………………………2 第二章 鎖相迴路基本架構與原理……………3 2.1 簡介………………………………………3 2.2 鎖相迴路基本操作原理…………………3 2.3 鎖相迴路一般考量………………………4 2.3.1 相位雜訊………………………5 2.3.2 突波……………………………6 2.3.3 鎖定時間………………………8 2.4 鎖相迴路組成電路介紹………………8 2.4.1 相位頻率檢測器………………9 2.4.2 充放電泵電路…………………12 2.4.3 迴路濾波器……………………15 2.4.4 電壓控制振盪器………………15 2.4.5 除頻器…………………………18 2.5 鎖相迴路的迴路分析…………………20 2.5.1 鎖相迴路線性轉移函數………20 2.5.2 鎖相迴路系統參數推導………22 2.6 整數型與分數型頻率合成器基本架構與原理……………27 2.6.1 整數型頻率合成器……………28 2.6.2 分數型頻率合成器……………29 2.7 結論……………………………………31 第三章 串接式雙迴路三角積分調變分數型頻率合成器架構與模擬……………33 3.1 簡介…………………………………………………………33 3.2 串接式雙迴路頻率合成器…………………………………34 3.3 注入鎖定式倍頻器…………………………………………36 3.4 串接式雙迴路三角積分調變分數型頻率合成器…………37 3.4.1 注入鎖定式倍頻器設計…………………………39 3.4.2 相位頻率檢測器設計……………………………41 3.4.3 充放電泵電路設計………………………………44 3.4.4 迴路濾波器電路設計……………………………47 3.4.5 可程式控制除頻器電路設計……………………47 3.4.6 電壓控制振盪器電路設計………………………53 3.4.7 三角積分調變器…………………………………58 3.5 串接式雙迴路三角積分調變分數型頻率合成器雜訊分析……………61 3.6 串接式雙迴路三角積分調變分數型頻率合成器模擬……72 3.7 結論…………………………………………………………75 第四章 應用於長期演進技術分數型頻率合成器…………………77 4.1 簡介…………………………………………………………77 4.2 串接式雙迴路三角積分調變分數型頻率合成器量測……80 4.2.1 量測設定…………………………………………80 4.2.2 量測結果…………………………………………81 4.3 結論…………………………………………………………96 第五章 總結與未來展望……………………………………………101 參考文獻………………………………………………………………103 作者簡介………………………………………………………………107

    [1] 楊育哲, “CMOS單晶片分數型鎖相迴路頻率合成器之設計與應用”, 國立臺灣大學電子所博士論文, June. 2007.
    [2] P. Larsson, “A 2-1600MHz CMOS Clock recovery PLL with low-Vdd capability”, IEEE J. Solid-State Circuits, vol. 34,pp. 1951-1960, Dec. 1999.
    [3] W. Rhee, “Design of High Performance CMOS Charge Pumps in Phase-Locked Loops”, Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, pp. 545-548, 1999.
    [4] N. Nguyen and R. Meyer, “Start-up and frequency stability in high-frequency oscillators”, IEEE J. Solid-State Circuits, Vol. 27, No. 5, May. 1992.
    [5] Toby K. K. Kan, Gerry C. T. Leung, and Howard C. Luong, “A 2-V 1.8-GHz Fully-Integrated CMOS Dual-Loop Frequency Synthesizer”, IEEE J. Solid-State Circuits, VOL. 37, NO. 8, AUGUST 2002.
    [6] Z. Shu, K. L. Lee, and B. H. Leung, “A 2.4-GHz Ring-Oscillator-Based CMOS Frequency Synthesizer With a Fractional Divider Dual-PLL Architecture”, IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 452-462, March 2004.
    [7] Ye, Z., Chen, W., Kennedy, M. P., “A novel dual-loop multi-phase frequency synthesizer”, Proc. European Conference on Circuit Theory and Design, Seville, Spain, pp. 567–570, 8/07
    [8] T. Wu, P. Hanumolu, U. Moon, K. Mayaram, “An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications”, Proceedings of ISCAS, pp. 3986-3989, Kobe, Japan, May 2005
    [9] Hsiao-Chin Chen, Wei-Kan Lee, “Battery-less ASK/O-QPSK Transmitter for Medical Implants”, IET Electronics Letters, Volume 48, Issue 17, pp.1036-1038, Aug. 2012.
    [10] B. Mesgarzadeh and A. Alvandpour, “First-harmonic injection-locked ring oscillators”, Proc. IEEE Custom Integrated Circuit Conf. (CICC), pp.733 -736 2006
    [11] B. Razavi, “A study of injection locking and pulling in oscillators”, IEEE J. Solid-State Circuits, vol. 39, no. 9, pp.1415 -1424 2004
    [12] N. Fong, J.-O. Plouchart, N. Zamdmer, D. Liu, L. F. Wagner, C. Plett, and N. G. Tarr, “A 1-V 3.8–5.7-GHz wide-band VCO with differentially tuned accumulation MOS varactors for common-mode noise rejection in CMOS SOI technology”, IEEE Trans. Microw. Theory Tech., vol. 51, no. 8, pp. 1952–1959, Aug. 2003.
    [13] Ryan Lee Bunch and Sanjay Raman, “Large-signal analysis of MOS varactors in CMOS -Gm LC VCOs”, IEEE J. Solid-State Circuits, vol. 38, pp. 1325-1332, Aug. 2003.
    [14] M. H. Perrott, M. D. Trott, and C. G. Sodini, “A modeling approach for Delta-Sigma fractional-N frequency synthesizers allowing straightforward noise analysis”, IEEE J. Solid-State Circuits, vol. 37, pp.1028 -1038 2002
    [15] 3GPP TS 36.101, http://www.3gpp.org/ftp/specs/html-info/36101.htm
    [16] 3GPP, “Technical Specification Group Radio Access Network; User Equipment (UE) radio transmission and reception (Release 8)”, 3GPP TS 36.101 V8.5.1.
    [17] Yoohwan Kim, Byunghak Cho, Yoosam Na, “A Design of Fractional-N Frequency Synthesizer with Quad-Band (700 MHz/AWS/2100 MHz/2600 MHz) VCO for LTE Application in 65 nm CMOS Process”, Microwave Conference, 2009. APMC 2009. Asia Pacific.
    [18] Nakyoon Kim, Yong Moon, “A Study on Wide-band Frequency Synthesizer for Advanced Wireless Communication”, SoC Design Conference (ISOCC), 2011 International.
    [19] J. W. M. Rogers, F. F. Dai, M. S. Cavin, and D. G. Rahn, “A Multiband ΔΣ fractional-N Frequency Synthesizer for a MIMO WLAN Transceiver RFIC”, IEEE J. Solid-State Circuits, vol. 40, no. 3, pp.678 -689 2005
    [20] S. E. Meninger and M. H. Perrott, “A 1-MHz bandwidth 3.6 GHz 0.18-um CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise”, IEEE J. Solid-State Circuits, vol. 41, no. 4, pp.966 -980 2006
    [21] C.C. Hung, D.S. Shen, S.I. Liu, “A 40GHz Fractional-N Frequency Synthesizer in 0. 13μm CMOS”, IEEE RFIC Symp. Dig., pp. 295-298, June 2008.
    [22] C.-M. Hsu , M. Straayer and M. H. Perrott, “A low-noise wide-BW 3.6-GHz digital ΔΣfractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation”, IEEE J. Solid-State Circuits, vol. 43, no. 12, pp.2776 -2786 2008
    [23] C.-Y. Yang , C.-H. Chang , J.-H. Weng and H.-M. Wu, “A 0.5/0.8-V 9-GHz frequency synthesizer with doubling generation in 0.13μm CMOS”, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 2, pp.65 -69 2011
    [24] Shekhar, S. et al., “A 2.4GHz Extended-Range Type-I ΔΣ Fractional-N Synthesizer with 1.8MHz Loop Bandwidth and -110dBc/Hz Phase Noise”, IEEE Trans. Circuits and Systems-II; Express Briefs, vol. 58, no. 8, pp. 472-476, August 2011
    [25] Chih-Wei Yao, and Alan N. Willson, Jr., “A 2.8–3.2-GHz Fractional- Digital PLL with ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO”, IEEE J. Solid-State Circuits, VOL. 48, NO. 3, MARCH 2013

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