一種電路耦合預測模型應用於電路設計之全域放置利用生成對抗網路基於常微分方程求解器

簡易檢索 / 詳目顯示

回結果列表

研究生：	李泳誼 Yung-Yi Lee
論文名稱：	一種電路耦合預測模型應用於電路設計之全域放置利用生成對抗網路基於常微分方程求解器 A Predictable Coupling Effect Model for Global Placement Using Generative Adversarial Networks with an Ordinary Differential Equation Solver
指導教授：	阮聖彰 Shanq-Jang Ruan
口試委員:	阮聖彰 Shanq-Jang Ruan 方劭云 Shao-Yun Fang 林昌鴻 Chang-Hong Lin 沈中安 Chung-An Shen
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2021
畢業學年度：	109
語文別：	英文
論文頁數：	70
中文關鍵詞：	生成對抗學習、物理設計、全域放置、電路耦合效應、電子電路自動化設計
外文關鍵詞：	generative adversarial networks (GAN), physical design, global placement, coupling effect, electronic design automation (EDA)
相關次數：	點閱：200 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

電路耦合效應是電路實體設計中的重要問題之一，此問題通常是在繞線階段後，產生的線段資訊來做運算與分析，傳統演算法在求解的過程中會根據問題的不同而造成不同的運算複雜度。為了解決此議題，本文提出了一種用來降低耦合效應的全域放置基於生成對抗網絡模型，並且利用不同階層(order)的常微分方程求解器，用以在訓練時維持穩定度以及準確度。最終我們訓練後的模型在兩個ISPD11/DAC'12 Contest benchmark 上的實驗結果表明，此耦合效應偵測器(CEE)可以與Ground Truth的真實圖像達到91%的相似程度，並且與傳統的全域繞線例如NCTUgr相比，速度提高了50倍。除此之外，我們的全域放置器(CFGP)是基於DREAMPlace的框架下所設計的，在利用耦合效應估計器的狀況下，與原本沒利用耦合效應估計器的情況下，我們的全域放置器降低了1.16倍的耦合效應。

One of the most critical issues in physical design is coupling capacitance. However, the issue is typically addressed during the routing stage, which necessitates the execution of a time-consuming algorithm. Based on the generative adversarial networks (GAN) model, we propose a coupling-free global placement (CFGP) model with different orders of ordinary differential equations (ODE) solver. Experiments on the ISPD’11/DAC’12 contest benchmark revealed that using the ODE-GAN architecture, our coupling effect estimator (CEE) model can achieve 0.91X similarity to the ground-truth image and a 50X speedup over traditional global routers such as NCTUgr. Compared to the original framework without the CEE model, the CFGP implemented using DREAMPlace results in a 1.38X reduction in coupling effect.

摘要    IV
ABSTRACT    V
ACKNOWLEDGEMENTS    VI
TABLE OF CONTENTS    VIII
LIST OF FIGURES    XII
LIST OF TABLES    XIV
CHAPTER 1    1
INTRODUCTION    1
CHAPTER 2    7
RELATED WORKS    7
2.1    The Place/RePlAce Algorithm Based on the DREAMPlace GPU-Toolkit Framework    7
2.2    Coupling Analysis    10
CHAPTER 3    11
PROPOSED METHOD    11
3.1    Overall Flow    11
3.2    Coupling Effect Estimtor (CEE)    14
3.2.1    Data Prepossessing    14
3.2.2    Feature Extraction    16
3.2.3    ODE-GAN    17
3.3    Coupling Free Global placement (CFGP)    20
3.3.1    CEE Forward/Backward flow    20
3.3.2    Cell Spreading    21
CHAPTER 4    22
EXPERIMENTAL RESULTS    22
4.1    Environment/Dataset Setup    22
4.2    Evaluation    24
4.2.1    Similarity of CSM and Ground-Truth    24
4.2.2    The performance of CFGP    26
4.3    Comparison    27
4.3.1    Cells spreading    27
4.3.2    Coupling segment map (CSM)    28
CHAPTER 5    30
CONCLUSIONS    30
REFERENCES    32
APPENDIX 1 – TRAINING PHASE OF CSM (1)    37
APPENDIX 2 – TRAINING PHASE OF CSM (2)    38
APPENDIX 3 – TRAINING PHASE OF CSM (3)    39
APPENDIX 4 – TRAINING PHASE OF CSM (4)    40
APPENDIX 5 – TRAINING PHASE OF CSM (5)    41
APPENDIX 6 – TRAINING PHASE OF CSM (6)    42
APPENDIX 7 – TRAINING PHASE OF CSM (7)    43
APPENDIX 8 – TRAINING PHASE OF CSM (8)    44
APPENDIX 9 – TRAINING PHASE OF CSM (9)    45
APPENDIX 10 – TRAINING PHASE OF CSM (10)    46
APPENDIX 11 – DAC’12 BENCHMARK MACRO (1)    47
APPENDIX 12 – DAC’12 BENCHMARK MACRO (2)    48
APPENDIX 13 – DAC’12 BENCHMARK MACRO (3)    49
APPENDIX 14 – DAC’12 BENCHMARK MACRO (4)    50
APPENDIX 15 – DAC’12 BENCHMARK MACRO (5)    51
APPENDIX 16 – RUDY PICTURE (1)    52
APPENDIX 17 – RUDY PICTURE (2)    53
APPENDIX 18 – RUDY PICTURE (3)    54
APPENDIX 19 – RUDY PICTURE (4)    55
APPENDIX 20 – RUDY PICTURE (5)    56



                                

[1] I. -R. Jiang, Y.-W. Chang, and J.-Y. Jiu, “Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 9, pp. 999–1010, 2000.
[2] R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, “Pattern routing: use and theory for increasing predictability and avoiding coupling, ”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 777–790, 2002.
[3] J. Lou and W. Chen, “Crosstalk-aware placement, ”IEEE Design & Test of Computers, vol. 21, no. 1, pp. 24–32, 2004.
[4] Z. Zhu, J. Chen, Z. Peng, W. Zhu, and Y.-W. Chang, “Generalized augmented lagrangian and its applications to vlsi global placement,” in 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), pp. 1–6, 2018.
[5] Y. Lin, Z. Jiang, J. Gu, W. Li, S. Dhar, H. Ren, B. Khailany, and D. Z. Pan, “Dreamplace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020.
[6] M. -K. Hsu, V. Balabanov, and Y.-W. Chang, “Tsv-aware analytical placement for 3-d ic designs based on a novel weighted-average wirelength model, ”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 4, pp. 497–509, 2013.
[7] C. Li and C. -K. Koh, “Recursive function smoothing of half-perimeter wirelength for analytical placement,” in 8th International Symposium on Quality Electronic Design (ISQED’07), pp. 829–834, 2007.
[8] W. C. Naylor, R. Donelly, and L. Sha, ”Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer,” US, 2001.
[9] T. F. Chan, J. Cong, J. R. Shinnerl, K. Sze, and M. Xie, “mpl6: enhanced multilevel mixed-size placement,” in Proceedings of the 2006 international symposium on Physical design, pp. 212–214, 2006.
[10] J. Lu, P. Chen, C. -C. Chang, L. Sha, J. Dennis, H. Huang, C. -C. Teng, and C. -K. Cheng, “eplace: Electrostatics-based placement using fast fourier transform and nesterov’s method,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 20, no. 2, pp. 1–34, 2015.
[11] Z. Xie, Y.-H. Huang, G. -Q. Fang, H. Ren, S.-Y. Fang, Y. Chen, and J. Hu, “Routenet: Routability prediction for mixed-size designs using convolutional neural network,” in 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1–8, 2018.
[12] A. Mirhoseini, A. Goldie, M. Yazgan, J. W. Jiang, E. Songhori, S. Wang, Y.-J. Lee, E. Johnson, O. Pathak, A. Nazi et al., “A graph placement methodology for fast chip design,” Nature, vol. 594, no. 7862, pp. 207– 212, 2021.
[13] W. Lu, Y. Zhang, Q. Zhang, X. Zhang, and Y. Li, “Litho-neuralode: Improving hotspot detection accuracy with advanced data augmentation and neural ordinary differential equations,” in Proceedings of the 2020 on Great Lakes Symposium on VLSI, pp. 387–392, 2020.
[14] D. Ding, B. Yu, J. Ghosh, and D. Z. Pan, “Epic: Efficient prediction of ic manufacturing hotspots with a unified meta-classification formulation,” in 17th Asia and South Pacific Design Automation Conference. IEEE, 2012, pp. 263–270.
[15] H. Wang, K. Wang, J. Yang, L. Shen, N. Sun, H.-S. Lee, and S. Han, “Gcn-rl circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning,” in 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020, pp. 1–6.
[16] C. Qin, Y. Wu, J. T. Springenberg, A. Brock, J. Donahue, T. P. Lillicrap, and P. Kohli, “Training generative adversarial networks by solving ordinary differential equations,” arXiv preprint arXiv:2010.15040, 2020.
[17] K.-R. Dai, W.-H. Liu, and Y.-L. Li, “Nctu-gr: Efficient simulated evolution-based rerouting and congestion-relaxed layer assignment on 3-d global routing,” IEEE Transactions on very large scale integration (VLSI) systems, vol. 20, no. 3, pp. 459–472, 2011.
[18] N. Viswanathan, C. Alpert, C. Sze, Z. Li, and Y. Wei, “The dac 2012 routability-driven placement contest and benchmark suite,” in DAC Design Automation Conference 2012. IEEE, 2012, pp. 774–782.
[19] N. Viswanathan, C. J. Alpert, C. Sze, Z. Li, G.-J. Nam, and J. A. Roy, “The ispd-2011 routability-driven placement contest and benchmark suite,” in Proceedings of the 2011 international symposium on Physical design, 2011, pp. 141–146.
[20] P. Spindler and F. M. Johannes, “Fast and accurate routing demand estimation for efficient routability-driven placement,” in 2007 Design, Automation & Test in Europe Conference & Exhibition. IEEE, 2007, pp. 1–6.
[21] I. Goodfellow, J. Pouget-Abadie, M. Mirza, B. Xu, D. Warde-Farley, S. Ozair, A. Courville, and Y. Bengi. “Generative adversarial networks,” Communications of the ACM, vol. 63, no. 11, pp. 139-144, 2020.
[22] R. Haoxing, D. Z. Pan, and P. G. Villarubia, (n.d.). “True crosstalk aware incremental placement with noise map,” IEEE/ACM International Conference on Computer Aided Design, 2004.

全文公開日期 2026/10/05 (校內網路)
全文公開日期 2026/10/05 (校外網路)
全文公開日期 2026/10/05 (國家圖書館：臺灣博碩士論文系統)

簡易檢索 / 詳目顯示

相關論文