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研究生: 陳彥丞
Yan-Cheng Chen
論文名稱: 設計與實現一個基於二元有限域之橢圓曲線數位簽章之IP
Design and Implementation of an IP for Elliptic Curve Digital Signature Based on Binary Field
指導教授: 林銘波
Ming-Bo Lin
口試委員: 林書彥
Shu-Yan Lin
陳郁堂
Yu-Tang Chen
蔡政鴻
Cheng-Hung Tsai
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2022
畢業學年度: 110
語文別: 中文
論文頁數: 74
中文關鍵詞: 數位簽章二元域多項式基底蒙哥瑪利演算法非對稱式加密
外文關鍵詞: digital signature, binary field, Montgomery ladder algorithm, asymmetric encryption, polynomial basis
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在透過網際網路傳輸資料的過程,為了避免資料內容遭到第三方人士竊取,資料加密成了必要的手段。然而資料加密僅提供保護資料內容的作用,卻無法保證加密後的資料是否遭到竄改,因此數位簽章的功能變得重要許多,資料加密結合數位簽章後,不僅具有保護原始內容外洩的功用,還能同時保證資料完整性以及不可否認性的效用。
本論文設計三種不同安全強度的橢圓曲線數位簽章加密與解密晶片,其金鑰長度分別為283位元、409位元、571位元,並將橢圓曲線架構於二元有限域上。在數位簽章加解密晶片中,採用多項式基底作為資料表示法,將橢圓曲線的運算架構於映射座標系上,同時採用蒙哥瑪利階梯演算法降低純量運算的參數權重問題。在設計與實現方面,晶片內部透過串列傳輸介面輸入與輸出資料,並將設計以模組化與參數化的形式實現,使得未來在金鑰擴展的設計更為靈活。完成的設計結果,有兩種實現版本:低成本與高吞吐量,使用者可依據實際應用選擇適合的版本。
完成的橢圓曲線數位簽章設計分別使用FPGA與ASIC實現與驗證。在FPGA實現上,使用Xilinx公司的Virtex 7 FPGA元件,其模擬結果如下:加密的部分依照安全性低至高的工作頻率、資源使用量以及吞吐量分別為{156 MHz, 20132 LUTs, 1031 kbps}、{131 MHz, 24615 LUTs, 600 kbps}、{111 MHz, 34562 LUTs, 369 kbps},解密的部分則為{156 MHz, 35186 LUTs, 246 kbps}、{128 MHz, 42126 LUTs, 146 kbps}、{111 MHz, 68690 LUTs, 92 kbps}。在ASIC驗證方面,採用TSMC 0.18μm標準元件庫設計,工作頻率為100 MHz,晶片總面積為2685.3 μm× 2683.1 m,等效閘數量約為310318 gates。


Data encryption has become a necessary procedure to prevent the message breach during data transmission through the Internet. However, it can only protect the content of the message from being changed; it cannot guarantee whether the encrypted message has been tampered with. To attack such a problem, the techniques of digital signature and data encryption are combined together to prevent the leakage of the original content and to ensure the data integrity and non-repudiation of the data as well.
In this thesis, an IP of elliptic curve digital signature is designed and implemented in three different security strengths with the key length 283 bits, 409 bits, and 571 bits. The elliptic curve architecture is based on the binary finite field with polynomial-basis representation. All arithmetic operations are carried out over the projective coordinate. In addition, the elliptic curve point multiplication uses the Montgomery ladder algorithm to resolve the hamming weight problem of scalar k. In terms of the design and implantation, the IP receives and transfers messages through a serial interface, and the IP design is modularized and parameterized to make flexible the key extension in the future. The resulting IP has two different versions: the low-cost and the high-throughput. Hence, the user can choose the suitable IP for their applications.
The resulting IPs have been implemented and verified with both FPGA and ASIC technologies. In the FPGA technology, a Xilinx FPGA Virtex-7 device is employed. In the encryption part, the working frequency、resource utilization, and throughput are {156 MHz, 20132 LUTs, 1031 kbps}, {131 MHz, 24615 LUTs, 600 kbps}, {111 MHz, 34562 LUTs, 369 kbps} respectively, in terms of low-to-high security strength. In the decryption part, the working frequency、resource utilization, and throughput are {156 MHz, 20132 LUTs, 1031 kbps}, {131 MHz, 24615 LUTs, 600 kbps}, {111 MHz, 34562 LUTs, 369 kbps} respectively. In the ASIC technology, the TSMC 0.18-m standard-cell library is used. The resulting simulation frequency is 100 MHz. The total area is 2685.3 μm× 2683.1 m, equivalent to 310318 gates.

目錄 摘要 I ABSTRACT II 致謝 IV 圖目錄 VIII 表目錄 XI 演算法 XIII 第一章 緒論 1 1.1研究動機 1 1.2研究方向 1 第二章 橢圓曲線數位簽章系統 3 2.1公開金鑰加密技術 3 2.2橢圓曲線密碼系統 4 2.2.1橢圓曲線基礎定義 5 2.2.2橢圓曲線點運算 7 2.2.3橢圓曲線純量積運算 9 2.2.4相異座標系上的純量積運算 9 2.2.5蒙哥瑪利階梯演算法 11 2.2.6純量積運算效能比較 13 2.3數位簽章演算法 14 2.3.1數位簽章加密流程 14 2.3.2數位簽章解密流程 15 2.3.3數位簽章驗證原理 17 第三章 橢圓曲線二元域硬體電路 18 3.1 有限域加法運算 18 3.2 有限域平方運算 18 3.3 有限域倒數運算 19 3.3.1 擴展歐幾里德演算法 19 3.3.2 Itoh-Tsujii演算法 20 3.4 有限域乘法運算 23 3.5 模簡化運算 25 第四章 硬體架構模組設計 27 4.1數位簽章加密模組 27 4.1.1 數位簽章加密模組 29 4.1.2數位簽章解密模組 30 4.2橢圓曲線純量積運算模組 31 4.3映射座標轉換模組 33 4.4點運算模組 33 4.4.1仿射座標點運算模組 33 4.4.2映射座標點加運算模組 35 4.4.3倍點運算模組 36 4.5仿射座標轉換模組 37 4.5.1僅保留X軸座標 37 4.5.2保留X、Y軸座標 37 4.6加法運算模組 39 4.7倒數運算模組 39 4.8乘法運算模組 40 4.8.1基礎有限域乘法器 40 4.8.2卡拉楚巴乘法器 41 第五章 FPGA硬體驗證與實驗數據 43 5.1 FPGA設計實現與驗證 43 5.1.1功能模擬驗證 44 5.1.3 繞線後模擬 47 5.1.4 FPGA效能分析 49 5.2 CELL-BASE設計實現與驗證 51 5.2.1功能模擬驗證 52 5.2.2 邏輯閘階層模擬 52 5.2.3 佈局後模擬 53 5.2.4晶片佈局 54 第六章 結論與未來展望 56 參考文獻 57

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全文公開日期 2025/07/11 (國家圖書館:臺灣博碩士論文系統)
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