非對稱式加密技術在現代通信和資訊安全領域中扮演著關鍵角色，其中RSA演算法為最廣泛使用的非對稱式加密算法之一。然而，傳統的RSA加解密演算法必須執行大量運算，導致速度較慢，限制了在實際上的應用。為了解決此問題，在本論文中，我們提出一個結合蒙哥馬利演算法與進位旁路加法器的RSA加解密硬體架構，來加速模數乘法的計算，進而減少RSA加解密演算法的運算時間。
為了達到上述目標，論文中首先探討蒙哥馬利演算法的約簡、模乘和模冪運算。接著深入研究加法器與乘法器的設計原理，特別是進位旁路加法器與節省回合方式的乘法器等。最後將上述考量整合至RSA加解密演算法的架構設計中，包括加解密電路模組、蒙哥馬利模冪模組、金鑰運算模組、加法器架構和乘法器架構。通過功能與時序模擬驗證，證實了本論文提出的架構設計在性能上的優越性。
完成的架構設計分別使用FPGA及ASIC實現與驗證。FPGA部分使用Xilinx公司的Virtex 7 FPGA元件，其合成結果為269,671個LUTs及94,882個FFs。ASIC部分使用TSMC 0.18 μm 製程元件庫合成，合成結果等效1,419,160個NAND21邏輯閘，操作頻率皆為66.7 MHz，加解密最長花費時間為5.9 ms。

Asymmetric encryption techniques play a vital role in modern communication and information security, with the RSA algorithm being one of the most widely used such related algorithms. Nevertheless, the traditional RSA encryption/decryption algorithm needs a large amount of computations, thereby, leading to low throughput and limiting its practical applications. To solve this problem, in this thesis we propose an RSA hardware architecture that combines the Montgomery algorithm and carry-skip adders, to speed up the computations so as to reduce the RSA encryption/decryption execution time.
To achieve the above goal, we first explore the operations of Montgomery algorithm's reduction, modular multiplication, and modular exponentiation. Then, we study in depth the design principles of adders and multipliers; in particular, we focus on carry-skip adders and reduced-round multipliers. Finally, we combine the above considerations into the design of the RSA encryption/decryption architecture, including the encryption/decryption module, the Montgomery modular exponentiation module, the key operation module, the adder architecture, and the multiplier architecture. The resulting architecture has been proved to have superiority in performance through simulation verification in both function and timing.
The resulting architecture has been verified in both FPGA and ASIC. In FPGA verification, a Xilinx's Virtex 7 FPGA device is used and 269,671 LUTs and 94,882 FFs are consumed. In ASIC verification, the tsmc 0.18-μm process is employed and the synthesis result yields 1,419,160 NAND21 logic gates. Both implementations operate at a frequency of 66.7 MHz, with a maximum execution time 5.9 ms in both encryption and decryption operations.

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