隨著晶片封裝的接腳數愈來愈多、多電源域的廣泛使用使得封裝設計的複雜度和成本也逐漸提升。因此在封裝設計階段的電源供應網設計自動化也就更加重要了。由於晶片和基板製程的不同，封裝的電源供應網設計中可以使用大面積的鋪銅來保證電源完整性。然而，現今的鋪銅工作還是以工程師人工完成，耗費時間以及成本。我們提出電源層分割的自動化演算法來幫助完成封裝的電源供應網設計。更進一步提出兩個優化方法，使我們得到更符合需求的電源層分割結果。實驗結果顯示我們提出來之演算法可以成功產生電源層分割結果。

With the increasing pin number of chip packages and the widespread use of multiple power domains, the complexity and package design cost have gradually increased.
Therefore, the automation of power delivery network design in the package design stage is even more important.
Owing to the differences in chip and substrate manufacturing processes, a large copper area can be plated in the package-level power delivery network design to ensure power integrity.
However, these layout shapes are manually designed by engineers.
In this thesis, we propose an automated framework for power plane partitioning to help complete the initial package-level power delivery network design.
The framework consists of Steiner trees extraction, compatibility checking, and polygon generation algorithms to generate compatible power delivery layout partitioning.
Furthermore, two refinement methods are proposed, so that we can optimize power plane partitioning results in terms of layout shapes and source to target resistance.
The experimental results show that the proposed algorithm can successfully generate the power layer partitioning results.

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