隨著先進製程快速發展以及半導體產業的蓬勃發展，晶片大小也越來越小，因此有更多複雜的設計規則需要被遵守，而一個晶片在被下線之前必須沒有違反任何一個設計規則，這導致一個電路的可繞度就變得相對重要許多。此外，在現今電路設計中經常會有許多大型的巨集電路，而這些巨集電路所佔的面積比例甚至高達七成，因此如何擺放這些聚集電路就變得相當重要，此篇文獻中也證明了如何擺放巨集電路會大幅的影響到最後的可繞度，因此在此篇文獻中我們提出了第一個在擺放巨集電路階段直接考慮到可繞度的作品，我們運用機器學習建立了一個基於卷積神經網路的可繞度預測模型，並且成功運用退火演算法結合此模型在擺放巨集電路階段尋找最佳之巨集電路擺放方式，實驗結果顯示我們的作品能夠在擺放巨集電路階段準確的預測可繞度，並且找到良好的擺放巨集電路之方式，以及能夠大幅提高電路之可繞度。

With the dramatical shrink of feature size and the advance of semiconductor technology nodes, numerous and complicated design rules need to be followed, and a chip design can only be tapped-out after passing design rule check (DRC). The high design complexity seriously deteriorates design routability, which can be measured by the number of DRC violations after the detailed routing stage. In addition, a modern large-scaled design typically consists of many huge macros due to the wide use of intellectual properties (IPs). Empirically, the placement of these macros greatly determines routability, while there exists no effective cost metric to directly qualify a macro placement because of the extremely high complexity and unpredictability of cell placement and routing. In this paper, we propose the first work of routability-driven macro placement with deep learning. A convolutional neural network (CNN)-based routability prediction model is proposed and embedded into a macro placer such that a good macro placement with minimized DRC violations can be derived through a simulated annealing (SA) optimization process. Experimental results show the accuracy of the predictor and the effectiveness of the macro placer.

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