本論文之頻率合成器使用TSMC 0.18μm CMOS製程，以ISM頻段5.725-5.850 GHz為標的，設計振盪頻段5.2GHz ~ 5.4GHz之頻率合成器，其中通道間距8MHz。分別在迴路濾波器（Loop Filter，LPF）與Delta-Sigma 調變器(Δ-Σ Modulator)上加以設計，嘗試降低相位雜訊與簡化數位電路的複雜度；VCO使用傳統架構並利用在差動對共源端以LC並聯方式嘗試壓抑二次諧波。模擬結果顯示在5.3 GHz時之相位雜訊約-122dBc/Hz@1MHz，功耗約57.3mW。

This thesis presents a 5.2GHz ~ 5.4GHz 4th order PLL frequency synthesizer in TSMC 0.18μm CMOS process. The number of channels is 16 and the channel spacing is 8MHz. A novel loop filter structure is employed such that the design procedure is simplified. A hardware-simplified MASH 111Δ-Σ modulator is used in the frequency divider.
The VCO employs the conventional LC-type structure. A second parallel LC tank is connected in series with the VCO to suppress the common mode 2nd harmonic component. According to the simulation results, the phase noise performance at 5.3GHz is about -122 dBc/Hz@1MHz. The power consumption is about 57.3mW.

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