本論文實現一個使用單次二位元輔助之十位元漸進式類比數位轉換器(SAR ADC)。藉由使用單次二位元輔助之架構來減少轉換週期，進而提升類比數位轉換器的操作速度。動態邏輯電路(MdREG)減少了比較器輸出至數位類比轉換器(DAC)切換開關的延遲時間，可以減少所需的轉換時間。使用多個參考電位之電容式數位類比轉換器避免使用極小的單位電容，也減少了數位類比轉換器的整體電容值。抵補電壓之校正能有效地避免類比數位轉換器的線性度下降。
我們實現了兩個漸進式類比數位轉換器，它們是基於單次兩位元至單次一位元的架構。在180奈米製程下，實現的十位元、每秒一億次取樣之連續漸進式類比數位轉換器，其晶片面積為0.07平方毫米。在1.9伏特的操作電壓以及一億赫茲的取樣頻率下，類比數位轉換器消耗7.4毫瓦。而量測到的靜態效能，峰值微分非線性誤差(DNL)與峰值積分非線性誤差(INL)分別為-0.56/+0.67 LSB與-0.75/+0.79 LSB。量測到的奈奎斯特動態效能，訊噪失真比(SNDR)與無雜散動態範圍(SFDR)分別為52.2分貝與75.2分貝。另一個則是在40奈米製程下所實現的十位元、每秒五億次取樣類比數位轉換器。在0.9伏特的操作電壓以及五億赫茲的取樣頻率下，此類比數位轉換器消耗1.84毫瓦。模擬結果之下的奈奎斯特動態效能，訊噪失真比(SNDR)與無雜散動態範圍(SFDR)分別為59.6分貝與76分貝。

This thesis presents 2b/cycle-assisted 10-bit successive approximation register (SAR) analog-to-digital converters (ADCs). By applying 2b/cycle-assisted architecture, it reduces the number of conversion cycles and thus speeds up the ADC operation. The proposed dynamic register (MdREG) circuit cuts down the delay from the comparator output to the DAC switches. It also helps the ADC operate at higher sampling rates. Dual-reference C-DACs are proposed to avoid using a tiny unit capacitance. It also reduces the total capacitance of the digital-to-analog converter (DAC). The offset calibration scheme is proposed to effectively alleviate the degradation of the ADC linearity.
Two ADCs were implemented based on the proposed 2b-1b/cycle configuration. A 10-bit 100-MS/s SAR ADC was fabricated using a 180 nm CMOS technology. This ADC occupies an active area of 0.07 mm2. Operating at 100-MS/s, the ADC consumes 7.4 mW from a 1.9 V supply. The peak DNL and INL are -0.56/+0.67 LSB and -0.75/+0.79 LSB respectively. The measured Nyquist SNDR and SFDR are 52.2 dB and 75.2 dB respectively. Another 10-bit 500-MS/s ADC was implemented in 40nm CMOS. Operating at 500-MS/s, the ADC consumes 1.84 mW from a 0.9 V supply. The simulated Nyquist SNDR and SFDR are 59.6 dB and 76 dB respectively.

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