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研究生： 張永翰
Yung-Han Chang
論文名稱： 氮化鎵之單端輸出振盪器及CMOS注入鎖定除二除頻器之研究
Feedback GaN HEMT Oscillators and CMOS Divide-by 2 Injection-Locked Frequency Dividers
指導教授： 張勝良
Sheng–Lyang Jang
口試委員: 黃進芳
Jhin-Fang Huang
徐敬文
Ching-Wen Hsue
賴文政
Wen-Cheng Lai
張勝良
Sheng–Lyang Jang
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2018
畢業學年度： 106
語文別： 英文
論文頁數： 163
中文關鍵詞： 氮化鎵 、除二 、振盪器 、除頻器 、CMOS
外文關鍵詞： GaN, Oscillators, CMOS, Divide-by 2, Dividers
相關次數： 點閱：262  下載：0 
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    • 在RF射頻收發機中，PLL的特性非常重要，PLL內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)，而為了追求低功耗，低相位雜訊，與較寬的除頻範圍，在這其中又以壓控振盪器和注入鎖定除頻器特性最重要，而本論文主要研製鎖相迴路之注入鎖定除頻器與壓控振盪器。

    首先，第一部分我們呈現一個迴授振盪器，由穩懋GaN0.25μm製程實現，本次振盪器包含了HEMT amplifier跟LC feedback，在工作偏壓1.8V，電流為10.18mA，總功率消耗為18.33mW，在頻率7.26GHz的相位雜訊為-122.48dBc/Hz，總晶片面積為2*1mm2，FOM為-187.0 dBc/Hz

    接著，第二部份我們呈現一個作用在X頻帶的迴授振盪器，由穩懋GaN0.25μm實現，本次振盪器包含了HEMT amplifier跟LC feedback，本次使用的電感為一個並接的電感，並接的電感與傳統的電感差別在於Q值與感值在高頻的時候都比傳統的電感來的好，本電路的工作偏壓為2V，電流為10.8mA，總功率消耗為21.6mW，在頻率8.82GHz的相位雜訊為-124.95dBc/Hz，總晶片面積為2*1mm2，FOM為-189.56 dBc/Hz。

    第三部份我們呈現一個寬頻除二注入鎖定除頻器，使用台積電0.18 μm製程來實現，此除頻器使用中央抽頭式電感與寄生電容產生負阻抗，並採用單端注入訊號來實現。在Vdd的調整下，高注入功耗下會有四個頻帶產生，形成一個較寬除頻範圍。在驅動偏壓為0.65 V、注入功率為0 dbm時，注入鎖定頻率為3.21 ~ 10 GHz，鎖住範圍共6.79 GHz，百分比為102.8 %。此晶片面積為0.55 × 1.027 mm2，除頻器的核心功耗共3.263 mW。

    最後我們呈現一個寬頻除二注入鎖定除頻器，使用台積電0.18 μm製程來實現，此除頻器在注入功耗為0 dBm時會有雙頻帶，在Vbias 等於0.75V注入功率為0 dbm時，中心頻率為7.94GHz，注入鎖定頻率為2.2 ~ 10.14 GHz，鎖住範圍共7.94 GHz，百分比為128..68 %。此晶片面積為0.785 × 0.883 mm2，除頻器的核心功耗共4.57 mW。

    Communication system is include Baseband, Intermediate Frequency and Radio Frequency. RF transceiver is also called RFIC, which is a general term for processing all high-frequency electromagnetic waves, typically includes a Transceiver, Low Noise Amplifier (LNA), Power Amplifier (PA), Band pass Filter (BPF),Synthesizer, Mixer, PLL. PLL circuit include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD), In order to achieve low-power, low phase noise and wide Locking range, are the most important in VCO and Divider. This thesis presents the design of Injection-Locked Frequency Dividers (ILFDs) and HEMT Oscillator.

    First, a feedback GaN HENT oscillator is using a standard 0.25 μm GaN HEMT technology. The die area is 2 × 1 mm2. The oscillator consists of a HENT amplifier with an LC feedback. The power consumption of the oscillator core is 10.18 mW and the oscillator can generate single-ended signal at 7.26GHz and it also supplies output power 1.06dBm.At 1MHz frequency offset from the carrier the phase noise is -122.48dBc/Hz.

    Secondly, A feedback GaN HEMT oscillator implemented with the WIN 0.25 μm GaN HEMT technology is designed. The oscillator consists of a HEMT amplifier with an LC feedback network. With the supply voltage of VDD = 2 V, the GaN VCO current and power consumption of the oscillator are 10.8 mA and 21.6mW, respectively. The oscillator can generate single-ended signal at 8.82 GHz and it also supplies output power 1.24 dBm. At 1MHz frequency offset from the carrier the phase noise is -124.95 dBc/Hz. The die area of the GaN HEMT oscillator is 2×1 mm2.
    Thirdly, a wide locking range divide-by-2 with capacitive cross-coupled injection-locked frequency divider (ILFD) implemented in the TSMC standard 0.18 μm CMOS process. The ILFD is based on a differential VCO with one injection MOSFET for coupling the external signal to the resonator and uses a center-tapped inductor and parasitic capacitor to form the resonator. The die area is 0.550×1.027 mm2. The ILFD has four non-overlapped locking ranges at high injection power around 7 dBm. It also has wide locking range while non-overlapped locking range disappears.

    Finally, a wide locking range divide-by-2 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 um 1P6M CMOS process. The divide-by-2 ILFD targets for having two overlapped locking ranges at 0 dBm injection power. The 0.18 um 1P6M CMOS cross-coupled ILFD bases on a dual-resonance RLC resonator. At the drain-source bias of 0.75 V, and at the incident power of 0 dBm the locking range of the divide-by-2 ILFD is 7.94 GHz, from the incident frequency 2.2 to 10.14 GHz. At low injection power, the ILFD shows three non-overlapped locking ranges. The die area is 0.785 × 0.883 mm2.

    摘要 ㄧ Abstract 三 致謝 五 Table of Contents 六 List of Figures 九 List of Tables 一六 Chapter 1 Introduction 1 1.1 Background 1 1.2 Thesis Organization 4 Chapter 2 Principles and Design Considerations of Voltage Controlled Oscillators 6 2.1 Introduction 6 2.2 The Oscillators Theory 8 2.2.1 Feedback Oscillators 8 2.2.2 Resonator and Negative Resistance 11 2.3 The Classification of Oscillators 15 2.3.1 Ring Oscillator 15 2.3.2 LC-Tank Oscillator 22 2.4 Passive Components Design in VCO 36 2.4.1 Capacitor Design 36 2.4.2 Varactor Design 38 2.4.3 Inductor Design 45 2.4.4 Transformer Design 49 2.4.5 Resistor Design 58 2.5 The Basic parameters of VCO 59 2.5.1 RF Center Frequency [Hz] 59 2.5.2 RF Output Signal Power [dBm] 59 2.5.3 Power Dissipation [mW] 60 2.5.4 Harmonic/spurious [dBc] 60 2.5.5 Phase Noise 60 2.5.6 Tuning Range 64 2.5.7 Tuning Sensitivity [Hz/V] 66 2.5.8 Tuning Linearity 66 2.5.9 Quality Factor 67 2.5.10 Figure of Merit [dBc/Hz] 70 Chapter 3 Design of Injection Locked Frequency Divider 71 3.1 Principle of Injection Locked Frequency Divider 73 3.2 Injection Locking 75 3.3 Noise in ILOs 76 3.4 Locking Range 78 3.5 Model of ILFD General Case 81 Chapter 4 Principles and Appliance of Gallium Nitride 83 4.1 Introduction 83 4.2 Advantages and applications of GaN 85 Chapter 5 A Feedback GaN HEMT Oscillator 88 5.1 Introduction 88 5.2 Circuit Design 90 5.3 Measurement Results 93 Chapter 6 An X-Band Feedback GaN HEMT Oscillator 99 6.1 Introduction 99 6.2 Circuit Design 101 6.3 Measurement Results 104 Chapter 7 Multi-Band Locking Ranges in Divide-by-2 Injection-Locked Frequency Divider with One-chip Inductor 110 7.1 Introduction 110 7.2 Circuit Design 112 7.3 Measurement Results 114 Chapter 8 On-Chip Inductor Used as Distributed Resonator in Divide-by-2 Injection-Locked Frequency Divider 119 8.1 Introduction 119 8.2 Circuit Design 121 8.3 Measurement Results 123 Chapter 9 Conclusions 132 References 1

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