本論文提出一個具有2.97 ps時間解析度且量測範圍達389 ns之時間至數位轉換器(Time-to-Digital Converter, TDC)，TDC以計數器法實現。系統使用多相位之鎖相迴路(Phase-Locked Loop, PLL)提供高頻時脈，並透過相位內插之技巧以提高時間解析度，輸出結果為18位元之數位訊號供FPGA讀取。
鎖相迴路之輸出頻率可為10.24 GHz ~ 10.52 GHz，透過壓控環形震盪器(Voltage-Controlled Ring Oscillator, VCRO)產生8個相位的輸出，經由相位內插器(Phase Interpolator, PI)產生32個相位以提供TDC當作計數時脈。TDC將輸入的時間差透過32個12位元的計數器來計數脈波週期個數，最後透過數位邏輯電路以及FPGA交握電路輸出加總結果。
本晶片採用TSMC 90nm 1P9M CMOS製程來實現，除了數位邏輯電路以及FPGA交握電路透過Cell-Based設計流程來完成外，其餘電路包括鎖相迴路之相位頻率偵測器、充放電泵電路、壓控環形振盪器、自偏壓緩衝器、電流模式邏輯除法器、差動轉單端電路、脈波吞噬型除頻器以及TDC之相位內插器、控制電路、開關電路、栓鎖電路、計數器電路等皆採用Full-Custom設計流程實現。PLL參考時脈為20 MHz，FPGA交握電路操作時脈為10 MHz，在PLL輸出頻率為10.24 GHz ~ 10.52 GHz下TDC的時間解析度為2.97 ps ~ 3.05 ps，量測範圍達389 ns ~ 400 ns，系統功率消耗為200.6 mW，晶片面積約為1.527 mm^2。

A time-to-digital converter (TDC) with a time resolution of 2.97 ps and a detect range of 389 ns is proposed in this thesis. The TDC is implemented by using the counter method. The system uses a multi-phase phase-locked loop (PLL) to provide high-frequency clock, and uses phase interpolation techniques to improve time resolution. The output result is an 18-bit word.
The output frequency of the PLL is from 10.24 GHz to 10.52 GHz. The PLL generates 8-phase outputs through the voltage-controlled ring oscillator (VCRO). They are interpolated into 32-phase signals. These signals are clock signals for 32 sub-TDCs. Each sub-TDC counts the number of clock cycles through a 12-bit counter to measure the input time difference. The 32 sub-TDC outputs are interpreted as a high resolution time difference through a dedicated digital logic circuit.
The TDC chip was fabricated in TSMC 90nm 1P9M CMOS process. The digital logic circuit and the FPGA handshaking circuit were implemented by the Cell-Based design flow, the other part of the chip including the PFD, CP, VCRO, Buffer, CMLD, DTS, PSD in PLL and phase interpolator, control circuit, switches, latches, counters in TDC were implemented by the Full-Custom design flow. The reference clock of the PLL is 20 MHz, the operating frequency of the FPGA handshaking circuit is 10 MHz. The time resolution of the TDC is from 2.97 ps to 3.05 ps and the detectable range is from 389 ns to 400 ns. The total power consumption is 200.6 mW. The chip area is around 1.527 mm^2.

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