隨著積體電路系統的發展，對各種高解析度之轉換器需求也急速的增加，因此高精度數位至時間轉換器的地位也日漸重要，其最主要應用在許多自動測試儀器及晶片上，迄今已發展出各種不同的架構及電路形式，適用於各項測試機台儀器中。其中，游標卡尺法在追求高解析度上為眾多方法中之翹楚，由於一般數位至時間轉換器利用游標卡尺法來實現之目的係利用兩相近之參考頻率來達成高解析度目標，然而其量測範圍往往無法超過一個參考週期；本研究提出增加量測範圍之電路以解決量測範圍受限之缺點，並提高整體最佳解析度達到8.3ps，最寬脈波產生寬度達到1s以上；此外，為有效降低環境變異(PVT)之影響，利用兩組鎖相迴路(Phase-Locked Loop)來自動校準該二參考頻率之振盪週期以達成解析度不受影響之目的。本晶片以TSMC 0.35-um CMOS 2P4M標準製程，輸入操作頻率為1.83MHz，在輸入3.3伏特的工作電壓下，總功率消耗為80毫瓦，全部晶片面積為2.01mm2。

Ａ high accuracy Digital-to-Time Converter (DTC) is proposed in the thesis to fit the dramatically increased demand of nowadays VLSI test chips or advance test systems. Many kinds of DTC have been developed by researchers. Among those, the vernier DTC is the best one in some aspects. Originally, the vernier principle is applied to high resolution DTC by using two reference clock with very close frequencies to make the effective resolution equal to the period difference of the reference clocks. However, the operation range is usually limited to one reference period. The operation range limitation is successfully eliminated in the proposed DTC, and two phase-locked loops are utilized to alleviate the PVT sensitivity to achieve a resolution as fine as 9 ps. The realized operation range is 1s which can be extended to infinity theoretically.
This proposed chip have been implemented in a TSMC 0.35um 2P4M standard CMOS process. The reference clock frequency is designed to be 1.83 MHz, and the power consumption is 80mW under 3.3v single powersupply. The total chip size is 2.01mm2.

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