近年來，隨著無線通訊系統快速發展，各種頻率合成器被研發出來，又以單晶片系統(System-On-Chip)為主要趨勢。在整合各系統子電路時常出線操作時脈相位不同的情況，而導致輸出資料錯誤，因此需要鎖相迴路(Phase-Locked-Loop, PLL)來減少相位偏差，使得整合系統中各個子電路的時脈相位一致，減少輸出偏差。其內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)，而上述之中以壓控振盪器與除頻器為核心電路，因此本論文研究提出一氮化鎵製程之壓控振盪器與二種不同的除頻器。

首先，我們探討一個使用台積電CMOS 0.18微米製程之寬除頻範圍除四/除八注入鎖定除頻器。此除頻器使用CML (current-mode logic) 除二除頻器疊接使用電容交叉耦合式之除二/四注入鎖定除頻器所構成; CML則為在flip-flop啟用上緣clock輸出切換到輸入，以致於輸出頻率為輸入的一半；隨著更小的負載，CML具有較小的RC延遲，但需要提高電壓來補償下降的迴路增益，做為功耗與延遲之tradeoff。因此使用疊接ILFD和CML，直流和交流電流可以更有效使用。疊接的除頻器在不同的操作中選擇適當的頻率並以適度的直流消耗實現適度的頻帶寬。而除二/四除頻器做為線性混波器之用。在除4功能運作之下，功率消耗為7.26mW，注入訊號強度為0dBm，鎖定頻率範圍從5.5 GHz到10.5 GHz; 而在除8功能運作之下，功率消耗為8.17mW，注入訊號強度為0 dBm，鎖定頻率範圍從15.5 GHz到17.8 GHz，晶片面積為0.8044×0.72 mm2。

第二部分，本篇提出一個使用台積電CMOS 0.18微米製程之使用3維多層路徑串聯單一路徑電感結合交叉電合寬頻注入式除二鎖定除頻器。在注入功率為0 dBm 與2.58 mW功耗之下，鎖定頻率範圍從2.8 GHz到8.4 GHz，最高的FOM可以達到38.76，此電路之晶片面積為0.4446×0.9198 mm2。

最後，本篇提出一個使用穩懋0.25微米製程，來呈現一個使用HEMT之左手傳輸振盪器。1.6V供應電壓下，此輸出電路在2V之Buffer電壓能夠產生差分輸出信號3.818GHz並能夠輸出2.86dBm的輸出功率。在1MHz時候之相位雜訊為-131.73 dBc/Hz，計算所得到的FoM為-188.4 dBc/Hz，此電路的面積為2×1mm2。

Recently, various frequency synthesizers have been developed with the rapid development of wireless communication systems in which SOC (System-On-Chip) is the main trend of them. When integrating the sub-circuits in system, there are phase errors or clock skews which generate asynchronous phenomenon in different sub-circuit blocks that causing output data error started up. Therefore, we need a Phase-Locked-Loop (PLL) for reducing the phase and clock error to decrease the output data error. In the Frequency synthesizer, its blocks include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), and Frequency Divider (FD). Among of them, the Voltage Controlled Oscillator and Frequency Divider are the main circuit, so this thesis proposed the design GaN HEMT oscillator and two different of Injection-Locked Frequency Dividers (ILFDs).

First, this thesis study using a TSMC CMOS 0.18 μm technology to achieve a wide locking range of Injection-Locked Frequency Divider divide-by-4 or 8. This frequency divider uses divide-by-2 current-mode logic (CML) stacked on capacitive cross-coupled oscillator used as an LC divide-by-2 or 4 ILFD. CML switches the output to the input based on flip-flop upper edge clock so that the output frequency is half of the input; with smaller loads, CML has a smaller RC delay, but needs to increase the voltage to compensate for the falling loop gain as a tradeoff for power consumption and delay. Therefore, using stacked ILFD and CML, DC and AC current can be used more efficiently. The frequency divider can select the appropriate frequency in different operations and achieves a moderate frequency bandwidth with moderate DC consumption. Injection MOSFET in ÷2 and ÷4 frequency divider are used as linear mixers. In divided by 4, the power consumption is 7.26mW at the injection power 0dBm, the frequency divider has a locking range from 5.5 GHz to 10.5 GHz. And in divided-by-8 mode, the power consumption is 8.17 mW at the injection power 0dBm, the frequency divider has a locking range from 15.5 GHz to 17.8 GHz. This chip area of circuit is 0.8044×0.72 mm2.

Secondly, this research proposes a three-dimensional inductor consisted of 3 series single-path and multi-path inductors combined with a cross-capacitance coupling divide by 2 injection locked frequency divider by using a TSMC 0.18 μm CMOS technology. At the power consumption of 2.58 mW and at the input power of 0 dBm, the locking range is from 2.8 to 8.4 GHz, and the highest FOM can reach 38.76. The chip size is 0.4446 × 0.9198 mm2.

Finally, this thesis design a 0.25 μm GaN HEMT Oscillator with Left-Handed Transmission Filter. With the supply voltage of VDD = 1.6 V, this oscillator can generate differential signal at 3.818 GHz and it also supplies output power 2.86 dBm with buffer supply 3.0 V. At 1 MHz frequency offset from the carrier the phase noise is -131.73 dBc/Hz, and the FoM of the proposed oscillator is -188.4 dBc/Hz. The die area of the GaN HEMT oscillator is 2 × 1 mm2.

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