一個無量測範圍限制，具自我校準使用游標尺法之時間至數位轉換器被提出。提出了一個新的量測方式，在不需使用其它的內差電路，由兩組單級游標尺延遲線即可完成待測時間寬度的粗測與細測。同時我們借重鎖相迴路的自我校準能力，成功的抑制單級游標尺延遲線的電壓變異、溫度變異與製程變異。使得本時間至數位轉換器在不同環境因素下也能保有相同之解析度。本電路的解析度最高解析度高達37.5ps，實現於TSMC 2P4M 0.35um製程，晶片面積只有0.222mm2。經量測可以得到在量測範圍在0.1ns~35ns 量測間距300ps 其INL 在＋0.7∼-0.7LSB，展現了相當優秀的量測結果。量測頻率在1M/sec，解析度在50ps的情況下功率消耗100mW。

A monolithic Vernier-based time-to-digital converter (TDC) with 37.5ps time resolution and theoretically unlimited input range has been integrated in 0.35-m standard 2P4M CMOS technology. A single-stage Vernier delay line is used for both coarse and fine measurement without the need of any other interpolation circuit. The operation frequencies of Vernier delay line are stabilized against process variations and ambient conditions by a novel dual phase-locked loops circuit. The proposed TDC successfully eliminates the element mismatch, input range limitation, external bias adjustment and complicated calibration problems. The measured differential nonlinearity is 0.2LSB, and the measured integral nonlinearity after averaging 500 samples is 0.7LSB. The power consumption is 150mW, and the chip size is as small as 0.222mm2.

[1.1] Nissinen J., Palojarvi P., Kostamovaara J, “A CMOS receiver for a pulsed time-of-flight laser rangefinder,” ESSCIRC Conf., pp. 325–328, Sept. 2003.
[1.2] Keunoh Park, Jaehong Park, “20 ps resolution time-to-digital converter for digital storage oscilloscopes,” IEEE Nuclear Science Symp., Vol. 2, pp. 876-881, Nov. 1998.
[1.3] Tian Xia, Hao Zheng, Jing Li, Ginawi A, ”Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators,” IEEE Computer Society Annual Symp., pp. 218-223, May 2005.
[1.4] http://www.acam.de/Content/English/tdc_applications/distance.html
[1.5] Wei Chang , Mao-Hsing Chiang, and Poki Chen, “A Highly Accurate Cyclic CMOS Time to Digital Converter with Temperature Compensation”, The 14th VLSI Design/CAD Symposium, Aug. 2003.
[2.1] R.Nutt, “Digiatl time inervalometer,” Rev. Sci.Instrum, vol.39, no9, pp.1342-1345, 1968
[2.2] I. Nissinen, A. Mantyniemi, J. Kostamovaara, ”A CMOS time-to-digital converter based on a ring oscillator for a laser radar,” ESSCIRC Conf., pp.469–472, Sept. 2003.
[2.3] E. Raisanen-Ruotsalainen, T. Rahkonen, J. Kostamovaara, “An integrated time-to-digital converter with 30-ps single-shot precision,” J. IEEE Solid-State Circuits, Vol.35, pp.1507-1510, Oct. 2000.
[2.4] Brian K. Swann, Benjamin J. Blalock,Lloyd G. Clonts,David M. Binkley,James M. Rochelle,Eric Breeding,K. Michelle Baldwin,”A 100-ps Time-Resolution CMOS Time-to-Digital Converter for Positron Emission Tomography Imaging Applications”, J. IEEE Solid-State Circuits, Vol. 39, Nov. 2004.
[2.5] E. Raisanen-Ruotsalainen, T. Rahkonen, J. Kostamovaara, “A low-power CMOS time-to-digital converter,” IEEE J. Solid-State Circuits, Vol.30, pp.984–990, Sept. 1995.
[2.6] C. Poki, L. Shen-Iuan, W. Jingshown, “Highly accurate cyclic CMOS time-to-digital converter with extremely low power consumption,” IEEE Electronics Letters, Vol. 33, pp.858–860, May 1997.
[2.7] Wei Chang , Mao-Hsing Chiang, and Poki Chen, “A Highly Accurate Cyclic CMOS Time to Digital Converter with Temperature Compensation”, The 14th VLSI Design/CAD Symposium, Aug. 2003.
[2.8] Jozef Kalisz, Ryszard Szplet, Jerzy Pasierbinski,Andrzej Poniecki, ”Field-Programmable-Gate-Array-Based Time-to-Digital Converter with 200-ps Resolution,” IEEE Trans. IM, Vol. 46, Feb. 1997.
[2.9] J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, “Architecture of field-programmable gate arrays,” IEEE Proc. Vol. 81, pp.1013-1029, Jul. 1993
[2.10] S.D.Brown et al., ”Field-Programmable Gate Arrays,” Norwell, MA: Kluwer, 1992
[2.11]R.Pelka, J.Kalisz, and R.Szplet,”Nonlinearity correction of the integrated time-to-digital converter with direct coding,” IEEE Trans. IM, Vol.46, pp.449-452, Apr. 1997.
[2.12]Otsuji T.-i., “A picosecond-accuracy, 700-MHz range, Si bipolar time interval counter LSI,” IEEE J. Solid–State Circuits, Vol. 28, pp.941-947, Sept. 1993
[2.13]T. Rahkonen and J. Kostamovaara, “The use of stabilized CMOS delay line for the digitization of short time intervals,” IEEE J. Solid-State Circuits, vol. 28, pp. 887–894, Aug.1993.
[2.14]C. T. Gray, W. Liu, W. A. M. Van Noije, T. A. Hughes Js and R. K. Cavin III, ” A sampling technique and its CMOS implementation with 1 Gbs bandwidth and 25 ps resolution, “ IEEE J. Solid–State Circuits, Vol. 29, pp. 340-349, Mar. 1994.
[2.15]Piotr Dudek, Stanislaw Szczepan´ski, and John V. Hatfield, ”A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE J. Solid–State Circuits, Vol. 35, Feb., 2000.
[2.16]A.H. Chan, G.W. Roberts, “A deep sub-micron timing measurement circuit using a single-stage Vernier delay line,” IEEE Custom Integrated Circuits Conf., pp.77-80, May 2002
[2.17]M. S. Gobrics, J. Kelly, K. M. Roberts, and R. L. Summer, “A high resolution multihit time to digital converter integrated circuit,” IEEE Trans Nucl. Sci., vol. 44, pp. 379–384, June 1997.
[3.1] Rong-Jyi Yang, Shang-Ping Chen, Shen-Iuan Liu, ”A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet,” IEEE J. Solid–State Circuits, Vol. 39, pp. 1356-1360, Aug. 2004.
[3.2] Chih-Kong Ken Yang, Ramin Farjad-Rad, Horowitz, M.A., “A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling,” IEEE J. Solid–State Circuits, Vol. 33, pp.713–722, May 1998.
[3.3] Chih-Kong Ken Yang, Ramin Farjad-Rad, Horowitz, M.A., “A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling,” IEEE J. Solid–State Circuits, Vol. 33, pp.713–722, May 1998.
[3.4] J. S. Lee, W. K. Jin, D. M. Choi, G. S. Lee, S. Kim, “A Wide Range PLL for 64X Speed CD-ROMs & 10X Speed DVD-ROMs,” IEEE Tran., Vol. 46, pp. 487-493, Aug. 2000.
[3.5] B. G. Goldberg, “The evolution and maturity of fractional-N PLL synthesis,” Microwave J., vol. 39, no. 9, September 1996.
[3.6] V. Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra, “A 320MHz, 1.5 mW 1.35 V CMOS PLL for microprocessor clock generation,” IEEE J. Solid–State Circuits, Vol. 31, pp. 1715-1722, Nov. 1996.
[3.7] Kim, K. Lee, Y. Moon, D. K. Jeong, Y. Choi and H. K. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 691-700, May 1997.
[3.8] Maneatis, J.G., “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid–State Circuits, pp.1723-1732, Nov. 1996.
[3.9] Mansuri, M., Liu, D., Yang, C.-K.K., “Fast Frequency Acquisition Phase-Frequency Detectors for GSamples/s Phase-Locked Loops,” IEEE J. Solid–State Circuits, VOL. 37, NO. 10, pp.1331-1334, Oct 2002.
[3.10]Rhee, W., ”Design of high-performance CMOS charge pumps in phase-locked loops,” ISCAS, Vol. 2, pp545-548, June 1999.
[3.11]Jae-Shin Lee, Min-Sun Keel, Shin-Il Lim, Suki Kim, ”Charge pump with perfect current matching characteristics in phase-locked loops,” IEEE Electronics Letters, Vol. 36, pp.1907-1908, Nov. 2000.
[3.12]Adrian Maxim, “Low-Voltage CMOS Charge-Pump PLL Architecture for Low Jitter Operation,” ESSCIRC, pp.423-426 2002.
[3.13]Larsson, P, “A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability,” IEEE J. Solid–State Circuits, Vol.34, Dec. 1999.
[3.14]P. Larsson, “Measurement and analysis of PLL jitter caused by digital switching noise,” IEEE J. Solid-State Circuits, vol. 36, pp. 1113–1119, July 2001.
[3.15]A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 790–804, June 1999.
[3.16]Behzad Razavi, “Design of Analog CMOS Integrated Circuits” ,McGraw-Hill, 2001.
[3.17]N.M. Nguyen, R.G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuits, vol.27, pp. 810-820, May 1992.
[3.18]Kuo-Hsing Cheng, Wei-Bin Yang, “A low power, wide operating frequency and high noise immunity half-digital phased-locked loop,” IEEE Asia-Pacific Conf., pp.263-266, Aug. 2002
[3.19]In-Chul Hwang, Chulwoo Kim, Sung-Mo Kang, “A CMOS self-regulating VCO with low supply sensitivity,” IEEE J. Solid-State Circuits, vol. 39, pp.42-48, Jan. 2004.
[3.20]Y. Ji-Ren and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, Vol. 24, pp. 62- 67, Feb. 1989.
[3.21]Y. Ji-Ren and C. Svensson, “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings,” IEEE J. Solid-State Circuits, Vol. 32, pp. 62- 69, Jan. 1997.
[3.22]Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu, Shen-Iuan Liu, “New dynamic flip-flops for high-speed dual-modulus prescaler,” IEEE J. Solid-State Circuits, vol 33, pp1568-1571Oct. 1998
[3.23]Jri Lee,Behzad Razavi “A 40-GHz Frequency Divider in 0.18-um CMOS Technology,” IEEE J. Solid-State Circuits, Vol. 39, Apr. 2004
[3.24]Pfaff D., Huang Q, ”A quarter-micron CMOS, 1 GHz VCO/prescaler-set for very low power applications,” IEEE Custom Integrated Circuits Proc., pp.649-652, May 1999.
[3.25]Tiebout M., “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, Vol. 39, pp. 1170-1174, July 2004
[3.26]M. Mansuri, CK.K. Yang, “A Low-Power Low-Jitter Adaptive Bandwidth PLL and Clock Buffer,” IEEE International Solid-State Circuits Conf., Vol.1, pp. 430-505, 2003.
[3.27]Roland E. Best, “Phase-Locked Loop：Design, Simulations”, Third Edition, McGraw-Hall Inc, 1993.
[3.28]Shen-luan Liu, “Analysis and Design of Phase-Locked Loops”, Graduate Institute of Electronics Engineering National Taiwan University.
[3.29]Mozhgan Mansuri, ”Low-Power Low-Jitter On-Chip Clock Generation”, Dissertation, University of California Los Angeles, 2003.
[3.30]Shyh-Shyuan Sheu, “Design and Implementation of Low-Power and High-Noise-Immunity Phase-Locked Loop”, Tamkang University, 2002.
[3.31]Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001, ISBN-0-07-118839-8.
[4.1] A.H. Chan, G.W. Roberts, “A deep sub-micron timing measurement circuit using a single-stage Vernier delay line,” IEEE Custom Integrated Circuits Conf., pp.77-80, May 2002.
[4.2] Ram Singh Rana; Zhang Chen Jian,”A 2.4GHz dual-modulus divide-by-127/128 prescaler in 0.35 /spl mu/m CMOS technology,” IEEE RFIC Symp., pp.475-478, June 2003.
[4.3] N. Weste, K.Eshraghian, “Principles of CMOS VLSI design,” Addison Wesley,1993
[4.4] B. Razavi, “A study of injection pulling and locking in oscillators,” IEEE Custom Integrated Circuits Conf., pp.21-24, Sept. 2003
[6.1] Brian K. Swann,Benjamin J. Blalock,Lloyd G. Clonts,David M. Binkley,James M. Rochelle,Eric Breeding,K. Michelle Baldwin, “A 100-ps Time-Resolution CMOS Time-to-Digital Converter for Positron Emission Tomography Imaging Applications,” IEEE J. Solid-State Circuits, vol. 39, pp.1839–1852, Nov. 2004.
[6.2] K. Karadamoglou, N. P. Paschalidis, E. Sarris, N. Stamatopoulos, G.Kottaras, and V. Paschalidis, “An 11-bit high-resolution and adjustablerange CMOS time-to-digital converter for space science instruments,” IEEE J. Solid-State Circuits, vol. 39, pp. 214–222, Jan. 2004.
[6.3] E. Raisanen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, “An integrated time-to-digital converter with 30-ps single-shot precision,” IEEE J. Solid-State Circuits, vol. 35, pp. 1507–1510, Oct. 2000.
[6.4] P. Dudek, S. Szczepanski, and J. V. Hatfield, “A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line,” IEEE J. Solid-State Circuits, vol. 35, pp. 240–247, Feb. 2000.
[6.5] E. J. Gerds, J. Van der Spiegel, R. Van Berg, H. H. Williams, L. Callewaert, W. Eyckmans, andW. Sansen, “A CMOS time to digital converter IC with 2 level analog CAM,” IEEE J. Solid-State Circuits, vol. 29, pp.1068–1076, Sept. 1994.
[6.6] F. Bigongiari, R. Roncella, R. Saletti, and P. Terreni, “A 250-ps timeresolution CMOS multihit time-to-digital converter for nuclear physics experiments,” IEEE Trans. Nuclear Sci., vol. 46, pp. 73–77, Apr. 1999.
[6.7] Y. Arai and M. Ikeno, “A time digitizer CMOS gate-array with a 250 ps time resolution,” IEEE J. Solid-State Circuits, vol. 31, pp. 212–220, Feb. 1996.
[6.8] Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao, “A high-precision time-to-digital converter using a two-level conversion scheme,” IEEE Tran. Nuclear Sci., Vol. 51, pp.1349-1352, Aug. 2004