簡易檢索 / 詳目顯示

回結果列表
研究生： 邱百毅
BAI-YI CIOU
論文名稱： 應用於通訊系統之鎖相迴路與導管式類比/數位轉換器
PLL and Pipelined Analog-to-Digital Converter for Communication Systems
指導教授： 劉政光
Cheng-Kuang Liu
口試委員: 李修至
Hsiu-Chih Lee
莊敏宏
Miin-Horng Juang
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 82
中文關鍵詞： 鎖相迴路 、導管式類比/數位轉換器
外文關鍵詞： PLL, Pipelined ADC
相關次數： 點閱：381  下載：41 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 本論文提出應用於通訊系統中鎖相迴路相關的積體電路晶片實作，包含鎖相迴路製作、鎖相迴路於時脈與資料回復電路之應用、鎖相迴路應用於類比/數位轉換器。第一個晶片是以TSMC 0.35µm 2P4M CMOS製程實現，可應用於手機射頻發射機之鎖相迴路。本晶片以1.418×0.915 mm2的面積完成，可產生2.4105-GHz的穩定時脈，在偏移中心載波頻率1 MHz處所量測到的相位雜訊為-111.9 dBc/Hz。在3.3伏特的供應電壓下，總消耗功率為40.18 mW。
    第二個晶片是應用於光接收器之鎖相迴路式時脈與資料回復電路，除了採用鎖相迴路電路來完成時脈的回復之外，並利用萃取出來的時脈與一個決策電路來做資料的回復。以TSMC 0.18µm 1P6M CMOS製程實現，可產生2.418-GHz的穩定時脈，在偏移中心載波頻率1MHz處所量測到的相位雜訊為-115.34 dBc/Hz，在1.8&3.3伏特的電壓下功率消耗為75.5 mW , 晶片面積為1 .286×0.814 mm2。
    第三個晶片是8-bit 100 MS/s雙重取樣管線式類比/數位轉換器，可應用在無線通訊系統或數位電視上，以TSMC 0.35µm 2P4M CMOS製程實現。採用每級1.5-bit的架構，以提高整體類比/數位轉換器的運算速度，同時結合數位校正技術以增加比較器的偏移電壓容忍度。ADC使用的時脈很重要，應用鎖相迴路產生精準之時脈信號。利用雙重取樣保持電路與雙重取樣之乘法式數位/類比轉換器，使整體的類比數位轉換之Throughput Rate加倍，也因此降低對運算放大器規格的要求以及大幅降低整體電路的功率消耗。供以1.5伏特的電壓，共消耗51.52 mW。

    This thesis presents chips for communication systems, including the phase-locked loop, its application to the clock and data recovery circuit, and its application to the pipelined ADC. The first chip is a design of phase-locked loop for the radio frequency transceiver of the cell-phone. It is implemented by TSMC 0.35µm 2P4M CMOS technology. Occupying an area of 1.418×0.915 mm2, a 2.4105-GHz steady clock is achieved. The measured phase noise is –111.9 dBc/Hz at 1 MHz offset from the carrier. It consumes a power of 40.18 mW under 3.3V supply.
    The second chip is a PLL-based clock and data recovery circuit (CDR) for application to optical receiver. And a decision circuit is designed to regenerate data streams. Fabricated by TSMC 0.18µm 1P6M CMOS technology, a 2.418-GHz steady clock is achieved. The measured phase noise is –115.34 dBc/Hz at 1MHz offset from the carrier. The power consumption of CDR is 75.5 mW under 1.8&3.3V supply voltages. It occupies a core area of 1 .286×0.814 mm2.
    The third chip is an 8-bit, 100 MS/s, pipelined Analog-to-Digital Converter (ADC) with a double-sampling method. It can be applied to the IEEE 802.11a WLAN or HDTV. It is implemented by TSMC 0.35µm CMOS technology. A 1.5-bit/stage architecture is adopted for higher operating speed. Cooperating with digital error correcting technique, it tolerates higher comparator’s input offset voltage. The clocks used in the ADC are essential and is properly designed from the PLL. Double-sampling track-and-hold circuit and double-sampling multiplying digital-to-analog converter, make the output throughput rate fast. It reduces the requisition for operation amplifier specification and reduces the power consumption of the whole circuit. The pipelined ADC dissipates 51.52 mW with 1.5V supply voltage.

    論文摘要 III Abstract IV Contents V CHAPTER 1 Introduction 1 1.1 Motivation 1 1.2 Overview of this thesis 5 CHAPTER 2 Fundamentals of Phase-Locked Loop 6 2.1 Phase-locked Loop 6 2.2 System Analysis 6 2.2.1 PLL Noise Issues 6 2.2.2 Linear Model of PLL 9 CHAPTER 3 Circuit Implementation of the Phase-Locked Loop 12 3.1 System-level Behavioral Simulation 12 3.2 Circuit Implementation 13 3.2.1 PLL Architecture 13 3.2.2 Voltage-controlled oscillator 14 3.2.3 PFD and Charge Pump 17 3.2.4 Frequency Divider 18 3.3 Experimental results 19 3.3.1 PLL Transistor-Level Simulation Results 19 3.3.2 PLL Measurement Results 20 CHAPTER 4 Circuit Implementation of the Clock and Data Recovery 25 4.1 System-level Behavioral Simulation 25 4.2 Circuit Implementation 26 4.2.1 CDR Architecture 26 4.2.2 VCO 27 4.2.3 PD 29 4.2.4 Charge Pump 30 4.3 Experimental results 31 4.3.1 CDR Transistor-Level system simulation results 31 4.3.2 CDR Measurement Results 32 CHAPTER 5 Circuit Implementation of the Pipelined ADC 37 5.1 Circuit Implementation 37 5.1.1 Pipelined ADC Architecture 37 5.1.2 Track-and-Hold circuits 39 5.1.3 Multiplying-digital-to-analog converter 44 5.1.4 Class AB Operational Transconductance Amplifier 45 5.1.5 Voltage Bias Circuit 47 5.1.6 Bootstrapped MOS Switch 50 5.1.7 High-impedance negative-unity-gain buffer 51 5.1.8 Comparator 51 5.1.9 Non-overlapping Clocks Generator 54 5.1.10 Digital Error Correction Circuit 55 5.2 Experimental results 57 5.2.1 Transistor-Level Simulation Results & Measured Results 57 5.2.2 Simulation results of Pipelined ADC 58 CHAPTER 6 Conclusions and Future Perspectives 60 6.1 Conclusions 60 6.2 Future perspectives 61 References 64

    [1] S. Kim and Y. Kim, “A fractional-n PLL frequency synthesizer design, ” IEEE SoutheastCon 2005, Proceedings 8-10, pp. 84-87, April 2005.
    [2] Z. Li, W. Ni, J. Ma, M. Li, D. Ma, D. Zhao, J. Mehta, D. Hartman, X. Wang, Ken K. O, and K. Chen, “A Dual-Band CMOS Transceiver for 3G TD-SCDMA, ” in ISSCC 2007, Feb. 2007.
    [3] National Semiconductor Corporation LMX2502 datasheet.
    [4] L. Sumanen and K. Halonnen, “A single-amplifier 6-bit CMOS pipelined ADC converter for WCDMA receivers, ” in Proc. 2001 IEEE Int. Symp. Circuits Sysrem, Vol. 1, pp. 584-587, May 2001.
    [5] W. Chaloenlarp and A. Thanachayanont, “Low-voltage pipelined ADC using class-AB pseudo-differential OTA, ” IEEE International Symposium on Communications and Information Technology, vol. 1, pp. 128-132, Oct. 2004.
    [6] J. E. Rogers and J. R. Long, “A 10Gb/s CDR/demux with LC delay line VCO in 0.18µm CMOS, ” in ISSCC 2002, San Francisco, CA, pp. 254-255, Feb.2002.
    [7] R. E. Best, Phase-Locked Loop, 5th Edition, McGraw-Hill, 2003.
    [8] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University, 1998.
    [9] T. H. Lee and Ali Hajimiri, “Oscillator phase noise: a tutorial, ” IEEE J. Solid-State Circuits, vol.35, pp. 326-336, Mar. 2000.
    [10] C. H. Lu, “An Agile 5.2-GHz RF CMOS Frequency Synthesizer, ” Master Thesis, National Taiwan University, June 2004.
    [11] M. Brownlee, P. K. Hanumolu, K. Mayaram, and U. Moon, “A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning, ” IEEE J. Solid-State Circuits, vol. 41, pp. 2720-2728, Dec. 2006.
    [12] S. I. Liu, Theory and Application of Phase-Locked Loop, Department of Electrical Engineering National Taiwan University, 2005.
    [13] B. Razavi, RF Microelectronics, Prentice Hall PTR, 1998.
    [14] C. H. Heng and B. S. Song, “A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO, ” IEEE J. Solid-State Circuits, vol. 38, pp. 848-854, June 2003.
    [15] G. C. T. Leung and H. C. Luong, “A 1-V 5.2-GHz CMOS synthesizer for WLAN applications, ” IEEE J. Solid-State Circuits, vol. 39, pp. 1873-1882, Nov. 2004.
    [16] S. K. Singh, T. K. Bhattacharyya, and A. Dutta, “Fully integrated CMOS frequency synthesizer for ZigBee applications, ” 18th International Conference on VLSI Design, pp. 780-783, Jan. 2005.
    [17] J. Lee, “A 75-GHz PLL in 90-nm CMOS Technology, ” in ISSCC 2007, Feb. 2007.
    [18] S. Laventino, C. Samori, A. Bonfanti, A. Lacaita, and V. Boccuzzi, “Frequency dependence on bias current in 5 GHz CMOS VCOs: Impact on tuning range and flicker noise upconversion, ” IEEE J. Solid-State Circuits, vol. 37, pp.1003-1011, Aug. 2002.
    [19] H. N. Shanan and M. P. Kennedy, “A Technique to Reduce Flicker Noise Up-conversion in CMOS LC Voltage-controlled Oscillators, ” IEEE J. Solid-State Circuits, vol. 39, pp.123-126, Sept. 2004.
    [20] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
    [21] K. C. Chuang, “A design of Phase-Locked Loop for the application in optical transmitter, ” Master Thesis, National Taiwan University of Science and Technology, July 2006.
    [22] C. Y. Yang, G. K. Dehng, J. M. Hsu, and S. I. Liu, “New dynamic flip-flops for high-speed dual-modulus prescaler, ” IEEE J. Solid-State Circuits, vol. 33, pp. 1568-1571, Oct. 1998.
    [23] S. A. Yu and P. Kinget, “A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS, ” in ISSCC 2007, Feb. 2007.
    [24] Z. Shu, K. L. Lee, and B. H. Leung, “A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture, ” IEEE J. Solid-State Circuits, vol. 39, pp. 452-462, March 2004.
    [25] S. Shin, K. Lee and S. M. Kang, “Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors, ” IEEE International Symposium on Circuits and Systems, pp. 21-24, May 2006.
    [26] R. S. Rana, “Programmable low-noise fast-settling fractional-N CMOS PLL with two control words for versatile applications, ” IEE Proceedings Circuits, Devices and Systems, pp. 654-660, Dec. 2005.
    [27] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003.
    [28] J. Savoj and B. Razavi, High-Speed CMOS Circuits for Optical Receivers, Boston: Kluwer Publishers, 2001.
    [29] J. Savoj and B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector, ” IEEE J. Solid-State Circuits, vol. 36, pp. 761-768, May 2001.
    [30] J. Lee and M. Liu, “A 20-Gb/s Burst-Mode CDR in 90-nm CMOS, ” in ISSCC 2007, Feb. 2007.
    [31] B. Razavi, “Challenges in the design high-speed clock and data recovery circuits, ” IEEE Communications Magazine, vol. 40, pp. 94-101, Aug. 2002.
    [32] C. W. Yao and A. N. Willson, “A Phase-Noise Reduction Technique for Quadrature LC-VCO with Phase-to-Amplitude Noise Conversion, ” IEEE ISSCC 2006, Feb. 2006.
    [33] M. S. Yu, “Design and Application of a 1.25 Gb/s Clock and Data Recovery Circuit, ” Master Thesis, National Taiwan University, June 2002.
    [34] H. T. Ng, F. R. Ramin, M. J. E. Lee, W. J. Dally, T. Greer, J. Poulton, J. H. Edmondson, R. Rathi, and R. Senthinathan, “A Second-Order Semidigital Clock Recovery Circuit Based on Injection Locking, ” IEEE J. Solid-State Circuits, vol. 38, pp. 2101-2110, Dec. 2003.
    [35] R. J. Yang and S. I. Liu “A 1.7-3.125Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 2004.
    [36] M. H. Perrott, Y. Huang, R. T. Baird, B. W. Garlepp, L. Zhang, and J. P. Hein, “A 2.5Gb/s Multi-Rate 0.25μm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter, ” in ISSCC 2006, Feb. 2006.
    [37] R. J. Yang, K. H. Chao, S. C. Hwu, C. K. Liang, and S. I. Liu, “A 155.52Mbps~3.125Gbps Continuous-Rate Clock and Data Recovery Circuit, ” IEEE J. Solid-State Circuits, vol.41, pp.1380-1390, Jun. 2006.
    [38] D. Dalton, K. Chai, E. Evans, M. Ferriss, D. Hitchcox, P. Murray, S. Selvanayagam, P. Shepherd, and L. DeVito, “A 12.5Mb/s to 2.7Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback, ” in ISSCC 2005, Feb. 2005.
    [39] B. Razavi, Principles of Data Conversion System Design, IEEE Press, New York, 1995.
    [40] J. L. Fan, C. Y. Wang, and J. T. Wu, “A Robust and Fast Digital Background Calibration Technique for Pipelined ADCs, ” in IEEE Transactions on Circuits and Systems--I: Fundamental Theory and Applications : Accepted for future publication, 2007.
    [41] J. L. Fan and J. T. Wu, “A robust background calibration technique for switched-capacitor pipelined ADCs, ” in IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 1374-1377 , May 2005.
    [42] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter, ” IEEE J. Solid-State Circuits, vol. 38, pp. 599- 606, May 1999.
    [43] G. D. Dai, F. Liu, and Y. q. Zhuang, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter, ” in International Conference on Solid-State and Integrated Circuits Technology, vol. 2, pp. 1563-1566, Oct. 2004.
    [44] L. Sumanen, M. Waltari, and K. A. I. Halonen, “A 10-bit 200-MS/s CMOS Parallel Pipeline ADC Converter, ” IEEE J. Solid-State Circuits, Vol. 36, No. 7, July 2001.
    [45] S. Haider, A. Ghosh, R. s. Prasad, A. Chatierjeee, and S. Banerjee, “A 160MSPS 8-Bit Pipeline Based ADC, ”International Conference on VLSI Design, Jan. 2005.
    [46] A. Baschirotto, “A low-voltage sample-and-hold circuit in standard CMOS technology operating at 40 Ms/s, ”IEEE Trans. on Circuits and Systems-II, vol. 48, pp. 394-399, Apr. 2001.
    [47] T. S. Lee and C. C. Lu, “A 1.5V 50MHz Pseudo-Differential CMOS Sample-and-Hold Circuit with Low Hold Pedestal, ”IEEE Transactions on Circuits and Systems-I, Volume 52, pp.1752-1757, Sept. 2005.
    [48] A. Boni, A. Pierazzi, and C. Morandi, “A 10-b 185MS/s track-and-hold in 0.35-m m CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 195-203, Feb. 2001.
    [49] T. S. Lee and C. C. Lu, “A Very-High-Speed Low-Power Low-Voltage Fully Differential CMOS Sample-and-Hold Circuit with Low Hold Pedestal, ” IEEE International Symposium on Circuits and System, Vol. 4 pp. 3111-3114, May 2005.
    [50] S. T. Ryu, B. S. Song, and K. Bacrania, “A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse, ” IEEE J. Solid-State Circuits, vol. 42, pp. 475- 485, March 2007.
    [51] K. Honda, Ma. Furuta, and S. Kawahito, “A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline ADC Converter Using Capacitance Coupling Techniques, ” IEEE J. Solid-State Circuits, vol. 42, pp. 757- 765, April 2007.
    [52] W. J. Huang, “Design and Application of a 1.25 Gb/s Clock and Data Recovery Circuit, ” Master Thesis, National Taiwan University, July 2004.
    [53] W. Chaloenlarp and A. Thanachayanont, “Low-voltage pipelined ADC using class-AB pseudo-differential OTA, ” IEEE International Symposium on Communications and Information Technolog, , pp. 128- 132, Oct. 2004.
    [54] R. G. Carvaja1, J. Galan, J. Ramirez-hgulo, and A. Torralba, “New low-power low-voltage differential class-AB OTA for SC circuits, ” in IEEE Int. Symp. Circuits and Systems, Vol. 1, pp. 1589-592, May 2003.
    [55] O. Choksi and L. R. Carley, “Analysis of Switched-Capacitor Common -Mode Feedback Circuit ” IEEE Trans. Circuits and Systems, Vol. 50, Dec. 2003.
    [56] S. Wongnamkum and A. Thanachayanont, “New Class-AB Operational Transconductance Amplifier For High-speed Switched-Capacitor Circuits, ” IEEE International Symposium on Communications and Information Technologies, Oct. 2004.
    [57] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New York, 1997.
    [58] T. C. Hsueh, “The Design and Implementation of Low-Pass Multibit Delta-Sigma Modulators, ” Master Thesis, National Taiwan University, June 2001.
    [59] Y. C. Chen, “Switched-capacitor second-order Sigma-Delta modulator, ” Master Thesis, National Taiwan University of Science and Technology, July 2006.
    [60] C. J. B. Fayomi, G.. W. Roberts, and M. Sawan, “Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization” IEEE International Symposium on Circuits and Systems, Vol. 3, pp. 2200-2203, May 2005.
    [61] B. Wang, L. He, and M. Jones, “A low input, low-power dissipation CMOS ADC” International Symposium on Quality Electronic Design, pp. 27-29, March 2006.
    [62] T. S. Lee, L. D. Luo, and C. S. Lin, “Design techniques for a CMOS low-power low-voltage fully differential flash analog-to-digital converter” Midwest Symposium on Circuits and System, Vol. 1, pp. 357-360, July 2004.
    [63] T. M. Hancock, S. M. Pernia, and A. C. Zeeb, “A Digitally Corrected 1.5-Bit/Stage Low-Power 80 Ms/s 10-Bit Pipelined ADC” Electrical Engineering and Computer Science, University of Michigan, Dec. 2002.
    [64] Y. H. Park, S. Karthikeyaiz, F. Tsay and E. Bartoloine, “A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 V power supply” IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 580-583, May 2001.
    [65] T. H. Hsu, “A Low Spurious Tones of 5-GHz CMOS Frequency Synthesizer with New Current-Match Charge Pump, ” Master Thesis, National Chiao-Tung University, Dec. 2004.

    QR CODE