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研究生： 賴泓瑋
Hung-Wei Lai
論文名稱： 增強式注入寬鎖定三倍頻器與電流再利用除十六注入寬鎖定除頻器設計
Design of Injection-locked Frequency Tripler with Enhanced Wide Locking Range and Current-Reused Divide-by-16 Wide Injection-Locked Frequency Divider
指導教授： 張勝良
Sheng-Lyang Jang
口試委員: 莊敏宏
Miin-Horng Juang
宋峻宇
Jiun-Yu Sung
李後璋
Hou-Zhang Li
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2021
畢業學年度： 109
語文別： 英文
論文頁數： 101
中文關鍵詞： 除頻器 、倍頻器 、壓控振盪器 、頻率合成器 、混頻器
外文關鍵詞： Frequency divider, Frequency Multiplier, VCO, PLL, ILFD, mixer
相關次數： 點閱：195  下載：22 
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    • 在RF射頻收發機中，頻率合成器扮演著重要的角色，其內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)、倍頻器(FM)然而頻率合成器可應用在頻率偏移調變(FSK)。因為要追求低功耗、低相位雜訊與寬鎖定範圍的除頻器和倍頻器特性，所以本篇論文呈現出各種高性能的注入鎖定倍頻器(ILFM)和注入鎖定除頻器(ILFD)的設計。

    第一部分設計由 0.18 μm BiCMOS 工藝製造的 LC-tank 注入鎖定三倍頻器 (ILFT)，描述了 ILFT 的電路設計、工作原理和測量結果。差分輸入輸出 ILFT 電路由一次諧波注入鎖定振盪器 (ILO) 和一個三倍頻的混頻器所組成，用於 ILO 提供注入信號。ILO 的自由振盪頻率約為 4.6 GHz。在 9.52 mW 的直流功耗和 0 dBm 注入強度下，鎖定範圍是注入頻率 1.12GHz 到 1.8GHz，以提供頻率從 3.36GHz 到 5.4GHz (46.57%) 的輸出信號源。整個晶片佔地面積小，1.1980×1.2 mm2。使用先進設計系統（ADS）模擬顯示電感的峰值增加了注入鎖定三倍頻器範圍。此外，此三倍頻器也可以使用於低頻段或高頻段去應用於解調器中的頻率對振幅轉換器。

    設計的第二部分 CMOS 除十六注入鎖定除頻器 (ILFD) 是由一個除四電流模式邏輯 (CML) 的除頻器 (FD) 堆疊在於 LC 的電容交叉耦合振盪器上除四的 ILFD。 TSMC 0.18 μm 1P6M CMOS 工藝中的除十六 ILFD 在 12.5mW 的功耗和 0 dBm 的注入信號功率 Finj 下具有 10.76 GHz 至 12.6 GHz 的鎖定範圍 (15.75%)。除十六ILFD 使用具有寬鎖定範圍的 CML FD 追踪來自 LC ILFD 輸出的輸入頻率，並佔用 1.2×1.198 mm2 的小面積。本章ILFD 還可以使用於除八和除二十四的模式下運用。

    設計的第三部分是研究對於 TSMC 0.18 μm 3P6M BiCMOS 工藝實現的諧波混頻器 LC 型除四注入鎖定除頻器 (ILFD) 進行仿真研究。除四 ILFD 使用混合三諧振 LC 共振腔，該共振腔由雙諧振分佈式螺旋電感和雙諧振變壓器耦合合併而成。在 4.27 mW 的功耗下，自由震盪振盪頻率為 2.78 GHz。在輸入功率為 0 dBm 時，鎖定範圍為 3.9 GHz (32.36%)，從 10.1GHz 到 14 GHz。晶片面積為 1.006 ×0.925 mm2。

    最後部分設計電流再利用達靈頓放大器倍頻電路。達林頓放大器疊加在倍頻器上。電流再利用電路接受來自壓控振盪器 (VCO) 的輸入信號。CMOS 21GHz VCO倍頻集成電路採用TSMC 0.18 μm 1P6M CMOS工藝製造，頻率可調範圍為20.9 GHz至22.39 GHz，功耗為14.756 mW。整個芯片只佔1.180×1.103 mm2的小面積。

    In the RF transceiver, frequency synthesizer plays an important role, its blocks include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), Frequency Divider (FD), Frequency Multiplier (FM) and frequency synthesizer can be used as a Frequency Shift Keying demodulate (FSK). In order to pursue low-power, low phase noise and wide locking range include of Divider and Multiplier, so this thesis presents the design of high performance Injection-Locked Frequency Multiplier (ILFM) and Injection-Locked Frequency Divider (ILFD).
    The first part of design LC-tank Injection Locked Frequency Tripler (ILFT) fabricated in 0.18 μm BiCMOS process and it describes the circuit design, operation principle and measurement results of the ILFT. The differential input and output ILFT circuit is made of a first-harmonic injection-locked oscillator (ILO) and a mixer-type frequency tripler to supply an injection signal to the ILO. The free-running frequency of the ILO is around 4.6 GHz. At the DC power consumption 9.52 mW and at the incident power of 0 dBm, the locking range is from the incident frequency 1.12GHz to 1.8 GHz to provide an output signal source from the frequency 3.36 GHz to 5.4 GHz (46.57%). The whole chip occupies a small area of 1.1980×1.2 mm2. Simulation shows the inductive peaking increases the tripler locking range. In addition, this frequency multiplier can be applied to a frequency to amplitude converter in a demodulator by using the low-band or high-band alone.
    The second part of design CMOS divide-by-16 Injection-Locked Frequency Divider (ILFD) with a divide-by-4 Current-Mode Logic (CML) Frequency Divider (FD) stacked on a capacitive cross-coupled oscillator used as an LC divide-by-4 ILFD. The divide-by-16 ILFD in the TSMC 0.18 μm 1P6M CMOS process has a locking range from 10.76 GHz to 12.6 GHz (15.75%) at the power consumption of 12.5mW and an external injected signal power Pinj of 0 dBm. The varactor-less divide-by-16 ILFD uses the CML FD with wide locking range to track the input frequency from the LC ILFD output, and occupies a small area of 1.2×1.198 mm2. The ILFD also can operate in the divide-by-8 and divide-by-24 modes.
    The third part of research carries out the simulation study on a harmonic mixer LC-type divide-by-4 Injection-Locked Frequency Divider (ILFD) implemented in the TSMC 0.18 μm 3P6M BiCMOS process. This divide-by-4 ILFD uses a hybrid triple-resonance LC-resonator merged of a dual-resonance distributed spiral inductor resonator, and a dual-resonance transformer-coupled resonator. At the power consumption of 4.27 mW, the free-running oscillation frequency is 2.78 GHz. At the incident power of 0 dBm, the locking range is 3.9 GHz (32.36%) from 10.1 to 14 GHz. The die area is 1.006 ×0.925 mm2.
    The final part of design current-reused Darlington-frequency doubler circuit. The Darlington amplifier stacks on a frequency doubler. The current-reused circuit accepts an input signal from a voltage-controlled-oscillator (VCO). The CMOS 21GHz VCO-frequency doubler integrated circuit is fabricated in the TSMC 0.18 μm 1P6M CMOS process, the frequency source is tunable from 20.9 GHz to 22.39 GHz at the power consumption of 14.756 mW. The whole chip occupies a small area of 1.180×1.103 mm2.

    摘要 I Abstract III 致謝 V Table of Contents VI List of Figures VIII List of Tables XV Chapter 1 Introduction 1 1.1 Background 1 1.2 Thesis Organization 3 Chapter 2 Principles and Design Considerations of Voltage Controlled Oscillators 5 2.1 Introduction 5 2.2 The Oscillators Theory 7 2.2.1 Feedback Oscillators (Two port) 8 2.2.2 Negative Resistance and Resonator (One port) 10 2.3 Category of Oscillators 13 2.3.1 Ring Oscillator 13 2.3.2 LC-Tank Oscillator 18 2.4 Design Concepts of Voltage-Controlled Oscillator 22 2.4.1 Parameters of a Voltage-Controlled Oscillator 23 2.4.2 Phase Noise 25 2.4.3 Quality Factor 31 Chapter 3 Design of Injection Locked Frequency Divider ……………………….33 3.1 Introduction 33 3.2 Principle of Injection Locked Frequency Divider 34 3.3 Locking Range 36 Chapter 4 Injection-locked Frequency Tripler with Enhanced Locking Range ………………………………………………………………………………..39 4.1 Introduction 39 4.2 Circuit Design 40 4.3 Measurement and Discussion 42 Chapter 5 Current-Reused Divide-by-16 Injection-Locked Frequency Divider ………………………………………………………………………………..51 5.1 Introduction 51 5.2 Circuit Design 52 5.3 Measurement and Discussion 59 5.4 Voltage-mode ÷16 ILFD 61 Chapter 6 Simulation of Injection-Locked Frequency Dividers Using AC-Voltage Switchable Transformer-Couple Resonator 68 6.1 Introduction 68 6.2 Circuit architecture of the ILFD 70 6.3 Circuit Simulation of the ILFD 71 Chapter 7 Current-Reused Frequency Doubler and Darlington Amplifier 80 6.1 Introduction 80 6.1 Circuit Design 81 6.1 Measure and Discussion 86 Chapter 8 Conclusions 92 References 94

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