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研究生: 鄭士豪
Shih-Hao Cheng
論文名稱: 複晶矽薄膜電晶體通道工程之研究
Study of Channel Engineering in Polycrystalline Silicon Thin-Film Transistors
指導教授: 莊敏宏
Miin-Horng Juang
口試委員: 劉政光
Cheng-Kuang Liu
葉文昌
Wen-Chang Yeh
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2005
畢業學年度: 93
語文別: 英文
論文頁數: 77
中文關鍵詞: 複晶矽薄膜電晶體通道摻雜
外文關鍵詞: Vt-implant
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  • 複晶矽薄膜電晶體 (Poly-Si TFTs) 在許多方面上的應用是非常引人注目的,例如記憶體、主動式液晶顯示器和數位相機等,原因不外乎是因為低溫複晶矽薄膜電晶體具有很高的電子移動率(field effect mobility),且高於非晶矽薄膜電晶體之移動率100倍以上。在本論文裡,我們使用四種不同通道摻雜濃度(undope,1×1016cm-3, 5×1016cm-3及1×1017cm-3)來改變N型通道複晶矽薄膜電晶體的驅動能力及元件特性,並利用TSUPREM-4製程模擬軟體和MEDICI元件特性模擬軟體來設計元件,希望能得到最佳的結果。
    在本論文中,我們使用固相結晶(SPC)的矽膜結晶方式與熱爐管活化來製作N通道複晶矽薄膜電晶體元件。我們討論了三種情況:(1)在典型結構下作比較,發現通道參雜濃度為5×1016cm-3時,在通道長度為5um時有較小的OFF狀態電流為0.39pA及最佳的ON/OFF電流比為3×108。當通道長度為1um時,擁有最佳元件特性的通道摻雜濃度變為1×1016cm-3,此時Ioff=90.4pA,ON/OFF電流比約為3×106。 (2)用Vt-植入方式來製作典型薄膜電晶體;它使用了相同劑量(1×1011cm-2)不同能量(15keV,30keV,45keV及60keV)來做觀察,發現植入能量為30keV的可以得到最佳驅動電流,但是其元件電特性則相差無幾;然而Vt-implant方式在通道長度越短的情況下,電性比起均勻摻雜薄膜有更好的特性。 (3)利用在相同LDD結構中,比較通道摻雜濃度對電性的影響;發現當通道長度在3um~5um之間下,OFF狀態電流隨著濃度增加而下降,同時ON/OFF電流比也隨之上升;但是當元件微縮後,OFF狀態電流最小將發生於濃度為5×1016cm-3;此外將閘極氧化層厚度縮小時,大致電性趨勢沒有改變,其驅動電流、OFF狀態電流以及ON狀態電流則均變大,但是ON/OFF電流比則降低。


    The poly-silicon thin film transistors (poly-Si TFTs) are attractive for many applications such as memory, active matrix liquid crystal displays (AMLCDs) and digital cameras. It is because of the electron mobility of poly-Si TFTs are about 100 times than these of the amorphous silicon (a-Si) TFTs. In this thesis, four different channel doping concentration (undope, 1×1016cm-3, 5×1016cm-3 and 1×1017cm-3) are used to change the driving ability and device characteristics of the n-channel poly-Si TFTs. And we use TSUPREM-4 process simulation and MEDICI device characteristics simulation to design the device. The goal of the study is to find the best electric characteristics results.
    In this dissertation, the following three different methods are proposed: (1) Typical structure TFTs with uniform doped film. (2) Typical structure TFTs with boron implantation (Vt-implant) method. (3) LDD structure TFTs with uniform doped film.
    (1) For the typical poly-Si TFTs with different channel doping concentration schemes, we find that the smaller OFF current and the best ON/OFF current ratio are obtained as the channel doping concentration is 5×1016cm-3 for Lch=5um. The OFF current is 0.39pA and the ON/OFF current ratio is 3×108. For short channel length of 1um, the channel doping concentration of owning the best device electric characteristics (Ioff=90.4pA and Ion/Ioff=3×106) is 1×1016cm-3 due to higher lateral electric field.
    (2) For the typical TFTs with Vt-implant method, we observe that the better current driving capability is occurred as the implantation energy is 30keV, but the device characteristics are almost same with different implantation energy in the same time. Besides, as the channel length is short, OFF current caused by the Vt-implant method is smaller than that by uniform doped film regime.
    (3) The same lightly doped drain (LDD) structure with different channel doping concentration is observed. As the channel doping concentration increases, OFF current decreases and ON/OFF current ratio increases for Lch=3um~5um. Nevertheless, as the device shrink in size (Lch=1um~ 2um), a boron channel doping concentration of 5×1016cm-3 has to smaller OFF-state current. Besides, the device characteristics trend is almost same as reducing the gate oxide thickness, and all of the driving current, OFF current and ON current would be become larger. But, ON/OFF current ratio would decrease.

    Abstract (in Chinese)……………………………………………………i Abstract (in English)……………………………………………………iii Acknowledgements....………………………………………………………v Contents....…………………………………………………………………vi Figure Captions....………………………………………………………viii Table Captions.....………………………………………………………xiii Chapter1. Introduction 1-1 Application and development of poly-silicon thin film transistors....1 1-2 TFTs leakage current mechanism…………………………………3 1-3 Motivation…………………………………………………………4 1-4 The thesis organization……………………………………………5 Chapter2. Parameters Extraction and Device Fabrication Process Flow 2-1 The re-crystallization of silicon thin film……………………………9 2-2 Definition of ON current and OFF current…………………………9 2-3 Subthreshold swing (SS) & Threshold voltage (Vth)………………10 2-4 Fabrication Process Flow 2-4-1 Process flow of the typical n-TFTs with uniform doped film…12 2-4-2 Process flow of the typical n-TFTs with Vt-implant…………14 2-4-3 Process flow of the LDD n-TFTs with uniform doped film…17 Chapter3. Results and Discussion 3-1 The typical n-channel thin film transistors (TFTs) with different channel doping concentration……………………………………23 3-2 The typical TFTs with the implantation of Boron in channel layer (Vt-implant)………………………………………………………26 3-3 The n-channel lightly doped drain (LDD) structure TFTs with different channel doping concentration……………………………28 Chapter4. Conclusions……………………………………………………………71 Reference……………………………………………………………73

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