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研究生: 尤智玉
JHIH-YU YU
論文名稱: 去耦合電容佈局策略研究以實現電源遞送網路之阻抗平坦化
Strategy Study of Decoupling Capacitor Placement for The Impedance Flatness of Power Distribution Network
指導教授: 林丁丙
Ding-Bing Lin
口試委員: 林丁丙
Ding-Bing Lin
吳宗霖
Tzong-Lin Wu
謝松年
Sung-Nien Hsieh
丘建青
Chien-Ching Chiu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2021
畢業學年度: 109
語文別: 中文
論文頁數: 50
中文關鍵詞: 電源完整性電源遞送網路目標阻抗阻抗平坦化去耦合電容擾動電壓
外文關鍵詞: Power Distribution Network, PDN, Decoupling Capacitor, Decap, Voltage Fluctuations
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  • 在印刷電路板上會有許多的元件,例如:電壓調節模組(Voltage Regulator Module, VRM)、積體電路(Integrated Circuit, IC),而在VRM附近會放置容值較大的Bulk電容,來保持電源供應電壓的穩定,IC附近則會放置一些去耦合電容,因為當IC內部做切換時,會產生較大的暫態電流,當暫態電流流經電路上的電阻、電感時,電源遞送網路的電壓會產生波動和變化,因此電路板的電源完整性設計在於要有良好的電源遞送網路。
    目前的電源遞送網路會將輸入阻抗設計低於目標阻抗之下,使IC能正常運作並降低暫態雜訊,然而,僅將輸入阻抗設計低於目標阻抗之下,但並沒有平坦化時,會發生擾動電壓相互疊加而導致暫態雜訊振幅變大,這種因為電源遞送網路阻抗不平坦產生的雜訊稱為Rogue Wave。
    因此本論文的重點是針對電源遞送網路的輸入阻抗盡可能地平坦化,就算擾動電壓相互重疊,也不會產生過大的暫態雜訊,以維持其電路之電源完整性。


    There are many components on the printed circuit board, such as: Voltage Regulator Module (VRM), Integrated Circuit (IC), etc. Bulk capacitors are placed near the VRM to keep the power supply voltage stable. Decoupling capacitors will be placed near the IC so that a large transient current will be generated, when the IC is switched. As the transient current flows through the resistance and inductance on the circuit, the voltage of the Power Distribution Network(PDN) will be fluctuated and changed. Therefore, power integrity(PI) design of the PCB must have a good PDN.
    The PDN will design the input impedance below the Target Impedance so that the IC can operate normally and reduce transient noise. However, the input impedance isonly designed to be lower than the target impedance, but the disturbance voltage will overlap each other and cause the transient noise amplitude to increase, when there is no flattening. This noise which generated by un-flatness impedance from PDN is called Rogue Wave.
    This thesis is focusing on making the input impedance of the PDN as flat as possible. In this way, even if the disturbance voltage overlaps each other, it will not produce excessive transient noise to maintain the power integrity of its circuit.

    摘要 i ABSTRACT ii 誌謝 iii 目錄 iv 圖目錄 vi 表目錄 ix 第一章 緒論 1 1.1研究動機與目的 1 1.2文獻探討 3 1.2.1最佳化PDN中去耦合電容數量 4 1.2.2利用相對重要性最佳化PDN中去耦合電容數量 8 1.2.3使用基因演算法最佳化PDN中去耦合電容數量 11 1.3論文架構 14 第二章 電源遞送網路設計基礎理論 15 2.1目標阻抗 15 2.2電源遞送網路設計 19 2.2.1方法一 19 2.2.2方法二 20 2.2.3方法三 22 2.3 Rogue Wave的成因 23 第三章 去耦合電容佈局策略 34 3.1去耦合電容之佈局 34 3.2去耦合電容特性分析 36 3.3去耦合電容之挑選 38 第四章 結果與討論 42 4.1案例討論 42 4.1.1案例一 (64 port) 42 4.1.2案例二 (100 port) 44 4.1.3案例三 (114 port) 45 4.2分析與討論 46 第五章 結論 47 參考文獻 48

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