電源遞送網路(Power Distribution Network, PDN)在印刷電路板(Printed
Circuit Board, PCB)上係指由電壓調節模組(Voltage Regulator Module, VRM)
遞送電源至積體電路(Integrated Circuit, IC)之路徑，其會包含許多元件。 隨著
IC 切換頻率越來越高，所產生的暫態電流流經電源遞送網路會導致電壓有
擾動變化，因此電路板上的電源完整性設計其一議題在於設計一個良好的電
源遞送網路。
為了保持電源供應的穩定，使 IC 能正常運作並降低其暫態雜訊， 會在
VRM 附近放置容值較大的 Bulk 電容， IC 附近則放置一些去耦合電容，並
將電源遞送網路之輸入阻抗設計低於目標阻抗之下。 然而， 輸入阻抗若在頻
域上的呈現不平坦，縱使已設計於目標阻抗下，仍然有可能因為擾動的電壓
相互疊加產生暫態雜訊，此一現象稱為 Rogue wave。
本論文將針對 Rogue wave 的問題， 對多個觀測點的電源遞送網路提出
一有效平坦化之方法， 並評估機器學習導入單一觀測點電源遞送網路的阻抗
平坦化之可能性。

With the switching frequency of IC higher, the impedance of the power
distribution network (PDN) becomes lower to maintain the power integrity. To stabilize
the supplement of power and let the IC work well and also lower the transient noise,
designing an input impedance of PDN, which is lower than the target impedance is
important. By putting some bulk capacitors near the VRM (Voltage Regulator Module)
and some decoupling capacitors (decaps) near the IC, the impedance of PDN can be
designed under the target impedance. However, if the profile of the impedance under
the frequency domain is not flat enough, it still could cause some worst-case transient
noise, called rogue-wave.
In this research, an efficient algorithm for designing a PDN with multiple
observation ports is proposed. The algorithm provides a way to avoid the problem of
the rogue wave by designing a flattened input impedance. This research also analyzes
the feasibility of applying a machine learning model with a classification-based deep
neural network (DNN) structure to the designing process for a single observation port
of PDN.

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碩士學位論文， 一百一十年七月