本論文主要研究電源遞送網路(Power Delivery Network, PDN)的輸入阻抗設計中，雖然有將阻抗設計在低於目標阻抗(Target Impedance)之下，但由於阻抗變化幅度過大，導致擾動電壓(Voltage Fluctuations)變化幅度也很大。在這樣的情況下，當負載端IC發生高低準位辨別錯誤時，擾動電壓彼此會互相重疊而變得更大，如此會使整個系統電路的電源完整性(Power Integrity, PI)受到影響。而在本文中，主要的PDN阻抗設計中心理念是透過萃取PDN的Z參數做運算，來找出相對重要性之擺放去耦合電容的位置(Decap Port)，並制定挑選合適去耦合電容(Decoupling Capacitor, Decap)的規則，來達到PDN阻抗平坦化的目標，降低擾動電壓的變化幅度，藉此抑制瘋狗浪(Rogue Waves)的現象。從頻域上觀察，此方法在頻率範圍從100 KHz至100 MHz，PDN整體阻抗皆抑制在目標阻抗之下，其中在100 KHz至5 MHz的頻寬範圍之阻抗平坦化程度約17.5%左右，遠勝商用軟體最佳化結果的阻抗平坦化程度約41.4%，平坦化程度改善了約24%。

This thesis mainly presents the input impedance design of the power delivery network (PDN). If the impedance profile is not flat while staying at or below the target impedance, the worst-case transient noise gets bigger, which affects the power integrity (PI) of the system circuit. In this research, the main idea of the impedance of the power delivery network design is to find the relative importance of the decap ports by the Z parameters of the PDN, creating the rules for selecting the appropriate decoupling capacitor to achieve the flat impedance of the PDN, thereby suppressing the Rogue Waves. From the frequency domain observation, this method can efficiently suppress the impedance of the PDN below the target impedance from 100 KHz to 100 MHz, and the ratio of the flatness is 17.5% from 100 KHz to 5 MHz, which is better than the optimized results created by the commercial software.

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