隨著半導體製程技術的進步，系統晶片 (SOC) 中使用的嵌入式記憶體容量與密度越來越高，而導致記憶體故障更容易發生。因此，記憶體的良率很大程度決定系統晶片的良率。單一位元故障占所有故障形態比例最高，針對此種故障形態，大部分的嵌入式記憶體使用錯誤更正碼 (ECC) 偵測並修正單一位元故障。近期，許多研究提出了結合錯誤更正碼和內建自我修復 (BISR) 的方法來提升記憶體的良率，藉由在記憶體的自我測試模式時將單一位元故障記錄起來，之後並不馬上使用備用元件將其修復，而是在正常模式時以錯誤更正碼將其成功修復。但並沒有針對隱性的多重錯誤 (Recessive Multiple Faults, RMFs) 提出解決辦法。
我們針對此問題提出新的架構，使用新的修復方法，加入了多重故障偵測電路，可辨別單一位元錯誤和多位元錯誤，並使用備用元件修復多位元錯誤與單一位元故障所組成的故障列，剩下的單一位元故障是由錯誤更正碼更正。徹底消除隱性的多重錯誤之問題，而能提升記憶體的可靠度，所提出的技術可與傳統內建自我修復架構結合。此外，我們使用模擬器進行分析，結果顯示修復率及良率有顯著的提升，對於一個 512 × 1024 的記憶體，在瑕疵 (Defect) 數目為4時，分別有兩個備用行及備用列的情況下，修復率可以高達98.8%。我們實現了一個 4K × 8 記憶體晶片設計，使用 TSMC Artisan 0.18μm 1P6M 製程，晶片面積為1.07 × 1.70 mm2。整體而言，我們的方案有更好的可靠度、修復率及良率，而硬體成本幾乎可以忽略。

As semiconductor process technology continues to progress, the density of embedded memory in system-on-a-chip (SOC) keeps increasing. Hence, memory failures are more likely to occur. As a result, the yield of embedded memory will dominate the yield of the whole chip. Single-cell faults occupy the highest proportion among all failure patterns. For single-cell faults, most embedded memories incorporate error correction codes (ECC) for detection and correction. Recently, many researchers propose methods which improve the fabrication yield of memories by integrating ECC and built-in self-repair (BISR) techniques. These works record single-cell faults in the self-test mode and do not use the spare elements to repair them immediately. Instead, we use the error correction codes to repair these faults in the normal mode. However, only few works propose solutions to deal with multiple faults which cannot be detected by using only one test element.

In this thesis, we propose a new repair architecture aiming at the problem of recessive multiple faults (RMF). A novel repair method is proposed to distinguish single-bit faults and multiple-bit faults. We use spare elements to repair multiple-bit faults and faulty columns consisting of single-bit faults. The remaining single-bit faults are corrected by the adopted error correction code. Therefore, we fix the problem of recessive multiple faults (RMF) and enhance the reliability of memories. The proposed techniques can be easily integrated with the conventional BISR architectures. Moreover, we develop a simulator to evaluate repair rates. Experimental results show that the repair rate and the yield can be improved significantly. We can achieve up to 98.8% repair rate for a 512 × 1024 memory with two spare rows and two spare columns and 4 defects injected. An experimental 4K × 8 memory chip is designed and implemented with TSMC 0.18 m 1P6M process. The die size is 1.07 × 1.70 mm2. To sum up, we propose a integrated BISR scheme which can achieve a better reliability level, repair rate and yield. Moreover, the hardware cost is almost negligible.

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