本論文提出一個實現於現場可程式化閘陣列(Field Programmable Gate Array, FPGA)並能夠抵抗製程、電壓與溫度(process-voltage-temperature, PVT)變異的時間至數位轉換電路(Time-to-digital converter, TDC)。本論文之TDC不但可以抵抗PVT變異，並且可以達到高解析度與寬廣的量測時間範圍。經過FPGA內建的鎖相迴路提供八個不同的時脈相位，達到58.3ps不受PVT變異影像的解析度，另外並加入偏移校準技術更進一步降低PVT變異對偏移量的影響。經過短線量測之後量測出本論文之TDC的差分非線性誤差為-0.36~0.41 LSB；積分非線性誤差為-0.28~0.29 LSB。並完整測試涵蓋0C到60C的運作功能驗證本論文TDC對抗溫度變異之效果。

A process-voltage-temperature (PVT) insensitive time-to-digital converter (TDC) realized with Field Programmable Gate Array (FPGA) is presented. The proposed TDC is aimed to provide a PVT-insensitive solution with high resolution and wide measurement range. With the aid of the phase locked loop (PLL) in the FPGA which provides 8 different clock phases, a resolution of about 58.3 ps can be achieved against PVT variations. The proposed TDC successfully eliminates the offset with a simple offset cancellation technique. The short-term measurement result for the differential nonlinearity (DNL) of this TDC is -0.36 ~ 0.41 LSB and the integral nonlinearity (INL) is -0.28 ~ 0.23 LSB. This TDC was tested to be fully functional over 0C to 60C ambient temperature range with extremely low resolution variations.

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