本論文設計一個高硬體效率無記憶體的AES加解密系統，著重於的電路架構實現，適合使用在高吞吐量與硬體資源較少的應用，特別是低功耗的系統。
本論文中金鑰擴展電路使用即時運算(on-the-fly)產生回合金鑰，取代了傳統的查表法；位元組替換(SubBytes)運算將數值從GF(28) 轉換到 GF( (24)2 )，以降低乘法反元素的硬體複雜度；混合行運算(MixColumn)運算，改進現有電路，使用更多平行化運算，減少運算的傳輸延遲；為了要讓加解密的回合運算可以共用，增加一個多工器，透過選擇運算路徑，使加解密可以在同一個回合運算硬體單元內完成。
由Xilinx ISE Design Suite 13.4軟體，使用型號XC6VLX240T的FPGA模擬，AES-128須11個clocks完成加解密，核心工作頻率為122.09MHz，加解密吞吐量為1420.7Mbps，slice使用量為5371，每百萬位元所付出的硬體成本(Mbps/Slice)為0.265。
另外在Altera DE2-115 FPGA平台上驗證，以比較從SD卡讀取圖片執行加解密，與MATLAB執行加解密的結果。

This thesis presents the architecture design of a high-efficient memoryless Advanced Encryption Standard (AES) encryption system. We focus on the system architecture. The proposed architecture is suitable for high throughput, lack of hardware resource and low-power applications.
In this thesis, the key expansion uses the on-the-fly technique to generate round key to replace the traditional look-up table. The Substitute Byte Transformation converts from GF(28) to GF((24)2) to reduce the hardware complexity of computing the multiplication Inverse. The MixColumns Transformation improves existing circuit using more parallel computing to reduce the transmission delay. In order to share the round operation, we add a multiplexer to select operation path so that the encryption and the decryption can share the same hardware unit.
The experiment results show that the proposed AES-128 cipher can work up to 122.09 MHz and it takes about 11 clocks to complete both encryption and decryption. The corresponding throughput rate is 1420.7 Mbps. The usage of slice is 5371, The Mbps per Slice is 0.265.
The cipher system was also verified on the Altera DE2-115 FPGA board. The hardware cipher output and the software cipher output are compared. Those results are exactly the same.

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