當傳統金氧半元件微縮化至深次微米製程,新的可靠性問題產生了。這其中包含了短通道效應、熱載子效應、閘極引起汲極漏電流。穿透式場效電晶體在高度微縮化時可以提供較小的短通道效應、小的熱載子效應、小的閘極引起汲極漏電流。一個基本的穿透式場效電晶體，包含了一端高摻雜n型汲極（源極）和一端高摻雜p型源極（汲極）。其電流乃由能隙間穿透產生的電子電洞對為主要貢獻。
到目前為止,穿透式場效電晶體仍有一些需要被解決的問題。此論文目的就是透過製程與元件的各項參數模擬分析來實踐獲得高性能的穿透式場效電晶體。這些參數包含通道長、基底層厚度、基底層摻雜濃度、源極與汲極佈植條件、閘極氧化層厚度、汲極偏壓、不同的基底層材質。某些參數的改變也確實使元件性能提升。例如,單晶矽鍺基底層的使用使得開啟狀態汲極電流被提升,再利用降低汲極端電壓的方式使得關閉狀態汲極電流下降。或者,某些離子佈植條件與佈植位置也能使關閉狀態汲極電流下降且同時開啟狀態汲極電流上升。
由於穿透式場效電晶體可如傳統金氧半場效電晶體一般用於邏輯電路上，並且他沒有太多其他製程上的改變，所以穿透式場效電晶體用來當互補式金氧半場效電晶體在低功率行動裝置上的應用是一個前瞻性的元件。

As MOS devices are scaled down to the deep-submicron process, new reliability problems emerge. These include short-channel effect, hot-carrier effects, and gate-induced-drain leakage (GIDL). The tunneling field effect transistor (TFET) provides less short-channel effect, little hot-carrier effect, and little GIDL in high scaling fabrication. A band to band tunneling field effect transistor consists of n+-drain (source) and p+-source (drain). The electron-hole pairs are generated by band to band tunneling.
So far, some issues of TFET are still need to be resolved. In this study, further study of various device parameters for obtaining high-performance TFET is carried out via process and device simulation. This simulation was investigated with various parameters for obtaining high-performance TFET. These parameters include channel length (with various sidewall spacer length), substrate thickness, substrate doping concentration, gate oxide thickness, various drain biases, and substrate materials.
The performance of device is really improved by some parameters. For example, the on-current is increased by use of single crystalline SiGe substrate and off-current is reduced by a smaller drain biases. On the other hand, certain simulation indicates off-current is reduced and on-current is increased by certain ion-implantation profile and location.
Since there are not too many additional process steps compare with MOSFET, the TFET is an advancing device for low-power mobile applications fabricated with the standard CMOS process flow.

[1] S.M Sze, “SEMICONDUCTOR DEVICES physics and Technology”, 2nd Edition, p.199
[2] Nirschl Th, Wang P-F, Webe C, Sedlmeir J, Heinrich R, and Kakoschke R, “The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes.”, IEDM technical digest, pp.195-198, 2004
[3] Th. Nirschl, St. Henzler, J. Fischer, M. Fulde, A. Bargagli-Stoffi, M. Sterkel, J. Sedlmeir, C. Weber, R. Heinrich, U. Schaper, J. Einfeld, R. Neubert, U.Feldmann, K. Stahrenberg, E. Ruderer, G. Georgakos, A.Huber, R. Kakoschke, W. Hansch, and D. Schmitt-Landsiedel, “Scaling properties of the tunneling field effect transistor (TFET):Device and circuit.”, Solid-state electronics, Vol. 50, pp.44-51, 2006
[4] Stanley Wolf, “SILICON PROCESSING FOR THE VLSI ERA”, Vol.3, p.559
[5] Stanley Wolf, “SILICON　PROCESSING FOR THE VLSI ERA”, Vol.3, p.198
[6] Stanley Wolf, “SILICON　PROCESSING FOR THE VLSI ERA”, Vol.3, p.211
[7] S.M Sze, “SEMICONDUCTOR DEVICES physics and Technology”, 2nd Edition, p.200
[8] S.M Sze, “SEMICONDUCTOR DEVICES physics and Technology”, 2nd Edition, p.202
[9] Eiji Takeda, Hideyuki Matsuoka, Yasuo Igura, and Shojiro Asai, “A band to band tunneling MOS device (B2T-MOSFET)”, IEDM, Vol. 88, pp.402-404, 1988
[10] Krishna Kuma Bhuwalka and Jorg Schulze “A simulation approach to optimize the electrical parameters of a vertical tunnel FET”, IEEE Tran. Electron Device, Vol.52, NO. 7, pp.1541-1547, 2005
[11] Kathy Boucart and Adrian Mihai Ionescu, “Double gate tunnel FET with ultrathin silicon body and high-k gate dielectric”, Solid-State Device Research Conference, pp.383-386, 2006
[12] Shockley W. and Hopper WW., “The surface controlled avalanche transistor.” , IEEE Tran. Electron Device, Vol.11, No.11, p.535, 1964
[13] Reddick W.M. and Amaratunga G.A.J, “Gate controlled surface tunneling transistor.”, High Speed Semiconductor Devices and Circuits, Vol.7, No.9, pp.490-497, 1995
[14] Banerjee S, Richardson W, Coleman J, and Chatterejee A, “A new three-terminal tunnel device.”, IEEE Electron Device Letters, Vol.8, No.8, pp.347–349, 1987
[15] Koga J. and Toriumi A., “Three-terminal silicon surface junction tunneling device for room temperature operation.” IEEE Electron Device Letters, Vol.20, No.10, pp.529-531, 1999
[16] Bhuwalka K.K., Schulze J.,and Eisele I., “Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering.”, IEEE Tran. Electron Device, Vol.52, No.5, pp.909-917, 2005
[17] Uemura T. and Baba T., “Direct gate-controlled NDR characteristics in surface tunnel transistor.” , Device Research Conference,Vol.20, No.22, pp.65-66, 1994
[18] Hansch W., Fink C., Schulze J., and Eisele I., “A vertical MOS-gated Esaki tunneling transistor in silicon.” , Thin Solid Films, p.369 and pp.387-389, 2000
[19] Tehrani S., Shen J., Goronkin H., Kramer G., Tsui R., and Zhu T.X., “Resonant interband tunneling FET.”, IEEE Electron Device Letters, Vol.16, No.12, pp.557-559, 1995
[20] Aydin C, Zaslavsky A, Luryi S, Cristoloveanu S, Mariolle D,
and Fraboulet D, “Lateral interband tunneling transistor in silicon-insulator.” Appl Phys Lett, Vol.84, No.10, pp.1780-1782, 2000
[21] Kawaura H., Sakamoto T., and Baba T. ,“Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal oxide semiconductor field effect transistors.” , Appl Phys Lett, Vol.76, No.25, pp.3810-3812, 2000
[22] Wang P-F, Nirschl Th, Schmitt-Landsiedel D, and Hansch W, “Simulation of the Esaki-tunneling FET.”, Solid-State Electron, pp.1131, 2003
[23] International technology road-map for semiconductor (ITRS), Available from: http://public.itrs.net