針對一個固態硬碟的全域及區域動態隨機記憶體的配置策略

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研究生：	葉柏辰 Po-Chen Yeh
論文名稱：	針對一個固態硬碟的全域及區域動態隨機記憶體的配置策略 A Global and Local DRAM Allocation Strategy for Solid-State Drives (SSDs)
指導教授：	吳晋賢 Chin-Hsien Wu
口試委員:	吳晋賢 Chin-Hsien Wu 陳維美 Wei-Mei Chen 林淵翔 Yuan-Hsiang Lin 林昌鴻 Chang Hong Lin
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2021
畢業學年度：	109
語文別：	中文
論文頁數：	70
中文關鍵詞：	快閃記憶體、動態DRAM分配、快閃記憶體轉換層
外文關鍵詞：	NAND Flash Memory, Dynamic DRAM Allocation, Flash Translation Layer
相關次數：	點閱：272 下載：23
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快閃記憶體(NAND Flash)擁有體積小、功耗低、抗震、存取速度快等優勢，但快閃記憶體仍會面臨資料的「異地更新」、「垃圾收集」和「不平衡的執行時間」等硬體上的限制。一般而言，在有限的DRAM空間中快閃記憶體轉換層(FTL)可以維護映射快取區存放經常存取的位址映射來處理「異地更新」和維護讀寫緩衝區存放經常存取的資料來處理「垃圾收集」和「不平衡的執行時間」，在論文中我們將提出針對一個固態硬碟的全域及區域動態隨機記憶體的配置策略，其中全域動態隨機記憶體配置的設計理念是透過最小快閃記憶體寫入量的期望值構建出期望值模型，計算出適當的DRAM空間分配給寫入緩衝區和寫入映射快取區。為了進一步減少快閃記憶體的讀取量，區域動態隨機記憶體配置的設計理念採用成本效益的策略將適當的 DRAM 空間分別從寫入緩衝區和寫入映射快取區重新分配到讀取緩衝區和讀取映射快取區，根據實驗結果，我們可以證明所提出的全域及區域動態隨機記憶體的配置可以比其他方法減少更多快閃記憶體中的讀/寫量來改善反應時間。

Although NAND flash memory has the advantages of small size, low-power consumption, shock resistance, and fast access speed, NAND flash memory still faces the problems of "out-of-place updates", "garbage collection" and "unbalanced execution time" due to its hardware limitations. Usually, a flash translation layer (FTL) can maintain the mapping cache (in limited DRAM space) to store the frequently accessed address mapping for "out-of-place updates" and maintain the read/write buffer (in limited DRAM space) to store the frequently accessed data for "garbage collection" and "unbalanced execution time". In the thesis, we will propose a global and local DRAM allocation strategy for solid-state drives (SSDs). The design idea behind the global DRAM allocation method is to calculate the suitable DRAM allocation for the write buffer and the write mapping cache by building an expected value model with a minimum expected value of writes for NAND flash memory. To further reduce reads in NAND flash memory, the design idea behind the local DRAM allocation method is to adopt a cost-beneﬁt policy to reallocate the proper DRAM space from the write buffer and the write mapping cache to the read buffer and the read mapping cache, respectively. According to the experimental results, we can demonstrate that the proposed global and local DRAM allocation can reduce more reads/writes in NAND flash memory than other methods to improve the response time.

Content
中文摘要
Abstract
Content
   Introduction
   Background Knowledge
1 Flash Translation Layer (FTL)
2 Write Buffer Mechanism
3 Regression Analysis
   Motivation and Related Work
1    Motivation
2    Related Work
   A Global and Local DRAM Allocation Strategy for Solid-State Drives (SSDs)
1    System Architecture
2    A Global DRAM Allocation Method for Write Buffer and Write Mapping Cache
2.1    Global Write Buffer Predictor
2.2    Global Write Mapping Cache Predictor
2.3    Global DRAM Allocator
3    A Local DRAM Allocation Method for Read Buffer and Read Mapping Cache
3.1    A Local Read Buffer Allocator (LRB allocator)
3.2    A Local Read Mapping Cache Allocator (LRMC allocator)
4    Different Designs for the Global and Local DRAM Allocation Methods
   Experimental Setup and Performance Evaluation
1    Experimental Setup
2    Experimental Results
2.1    Financial1
2.2    Financial2
2.3    Systor17-LUN0
2.4    Systor17-LUN1
2.5    Microsoft Research Cambridge (MSR)
2.6    Mixed Traces
   Conclusion
References


                                

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