During the last decade, Solid State Drives (SSDs) which are composed of multiple NAND flash chips are replacing the hard disk drives (HDDs) in the mass storage market because the faster throughout, lower power consumption and other advantages. Unfortunately, the reliability become a critical issue when designing a large-scale flash storage. In order to balance the performance and reliability, Redundant Arrays of Inexpensive Disks (RAID) storage architecture become necessary to flash memory storage. However, how to handle the overhead of parity page which is aggressively updated data is also a considerable problem. Besides, NAND flash memory enable to operate a small portion of MLC/TLC flash memory blocks in SLC-mode to serve as write buffer. These SLC-mode blocks can absorb a large number of write operations. In this paper, we present a novel RAID technique for reducing the flash memory write stress. The key idea is to adopt well-known delta compression with partial programming and use the partial parity technique. We leverage the partial programming of SLC-mode flash memory pages to make sure that the original data and updated data of the original ones can reside in the same physical page. Then we also implement a small cache and separate it to two parts to delay the original parity and delta partial parity. Coincidentally, the partial programming technique and partial parity delay scheme are both design for decreasing the total page write count including parity page on flash memory based RAID system and we make those two techniques cooperate well by managing efficiently different page format such as data page, parity page and delta page and so on. In this way, we can reduce the write stress of overall RAID system and also accompany less erase count. Those analysis are evaluated by using a SSD customized simulator. The results show that our proposed scheme can largely reduce the write stress and erase count on flash memory pages with significant hot intensive traces.

During the last decade, Solid State Drives (SSDs) which are composed of multiple NAND flash chips are replacing the hard disk drives (HDDs) in the mass storage market because the faster throughout, lower power consumption and other advantages. Unfortunately, the reliability become a critical issue when designing a large-scale flash storage. In order to balance the performance and reliability, Redundant Arrays of Inexpensive Disks (RAID) storage architecture become necessary to flash memory storage. However, how to handle the overhead of parity page which is aggressively updated data is also a considerable problem. Besides, NAND flash memory enable to operate a small portion of MLC/TLC flash memory blocks in SLC-mode to serve as write buffer. These SLC-mode blocks can absorb a large number of write operations. In this paper, we present a novel RAID technique for reducing the flash memory write stress. The key idea is to adopt well-known delta compression with partial programming and use the partial parity technique. We leverage the partial programming of SLC-mode flash memory pages to make sure that the original data and updated data of the original ones can reside in the same physical page. Then we also implement a small cache and separate it to two parts to delay the original parity and delta partial parity. Coincidentally, the partial programming technique and partial parity delay scheme are both design for decreasing the total page write count including parity page on flash memory based RAID system and we make those two techniques cooperate well by managing efficiently different page format such as data page, parity page and delta page and so on. In this way, we can reduce the write stress of overall RAID system and also accompany less erase count. Those analysis are evaluated by using a SSD customized simulator. The results show that our proposed scheme can largely reduce the write stress and erase count on flash memory pages with significant hot intensive traces.

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