[1] 黃惠群, ” 適用於生醫應用之低功耗可編程四通道類比感測前端電路與使用線 性提升技術之轉導電容濾波器”. 國立臺灣科技大學碩士論文, 2019.
[2] 蕭宗益, ” 類比記憶體編成之積體電路設計與系統整合”. 國立臺灣科技大學 碩士論文, 2015.
[3] D. Du and K. M. Odame, “A bandwidth-adaptive preamplifier,” IEEE Journal of Solid–State Circuits, vol. 48, no. 9, pp. 2142–2153, 2013.
[4] Z. J. Lo, Y. C. Wang, Y. J. Huang, and S. Y. Peng, “A reconfigurable differential-to single-ended autonomous current adaptation buffer amplifier suitable for biomedical applications,” IEEE Transactions on Biomedical Circuits and Systems, vol. 15, no. 6, pp. 1405–1418, 2021.
[5] S. Kim, J. Hasler, and S. George, “Integrated floating-gate programming environ ment for system-level ics,” IEEE Transactions on Very Large Scale Integration Sys tems, vol. 24, no. 6, pp. 2244–2252, 2016.
[6] T.-Y. Wang, M.-R. Lai, C. M. Twigg, and S.-Y. Peng, “A fully reconfigurable low noise biopotential sensing amplifier with 1.96 noise efficiency factor,” IEEE Trans actions on Biomedical Circuits and Systems, vol. 8, no. 3, pp. 411–422, 2014.
[7] T.-Y. Wang, L.-H. Liu, and S.-Y. Peng, “Power-efficient highly linear reconfigurable biopotential sensing amplifier using gate-balanced pseudoresistors,” IEEE Transac tions on Circuits and Systems II: Express Briefs, vol. 62, no. 2, pp. 199 – 203, 2015.
[8] S.-Y. Peng, L.-H. Liu, P.-K. Chang, T.-Y. Wang, and H.-Y. Li, “A power-efficient reconfigurable output-capacitor-less low-drop-out regulator for low-power analog sensing front-end,” IEEE Transactions on Circuits and Systems I: Fundamental The ory and Applications, vol. 64, no. 6, pp. 1318 – 1327, 2017.
[9] S.-Y. Peng, Y.-H. Lee, T.-Y. Wang, H.-C. Huang, M.-R. Lai, C.-H. Lee, and L.-H. Liu, “A power-efficient reconfigurable OTA-C filter for low-frequency biomedical applications,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 65, no. 2, pp. 543 – 555, 2018.
[10] T.-Y. Wang, H.-Y. Li, Z.-Y. Ma, Y.-J. Huang, and S.-Y. Peng, “A bypass-switching SAR ADC with a dynamic proximity comparator for biomedical applications,” IEEE Journal of Solid–State Circuits, vol. 53, no. 6, pp. 1743–1754, 2018.
[11] Z. J. Lo, B. Nath, Y. C. Wang, and S. Y. Peng, “A floating-gate-based four-channel reconfigurable analog front-end integrated circuit,” IEEE Proceedings of the Inter national Symposium on Circuits and Systems, pp. 1–4, 2021.
[12] K.-J. de Langen and J. H. Huijsing, “Compact low-voltage power-efficient oper ational amplifier cells for VLSI,” IEEE Journal of Solid–State Circuits, vol. 33, no. 10, pp. 1482–1496, 1998.
[13] J.Ramirez-Angulo, R.G.Carvajal, J. A. Galan, and A. Lopez-Martin, “A free but efficient low-voltage class-AB two-stage operational amplifier,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 53, no. 7, pp. 568–571, 2006.
[14] P. R. Surkanti and P. M. Furth, “Converting a three-stage pseudoclass-AB amplifier to a true-class-AB amplifier,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 59, no. 4, pp. 229–233, 2012.
[15] C. G.-Alberdi, J. A.-Ruiz, A. J. L.-Martin, and J. R.-Angulo, “Micropower class AB VGA with gain-independent bandwidth,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 60, no. 7, pp. 397–401, 2013.
[16] F. E.-Alfaro, S. Pennisi, G. Palumbo, and A. J. L.-Martin, “Low-power class-AB CMOS voltage feedback current operational amplifier with tunable gain and band width,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 61, no. 8, pp. 574–578, 2014.
[17] E. C.-Bernal, S. Pennisi, A. D. Grasso, A. Torralba, and R. G. Carvajal, “0.7-V three stage class-AB CMOS operational transconductance amplifier,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 63, no. 11, pp. 1807–1815, 2016.
[18] A. L.-Martin, M. P. Garde, J. M. Algueta, C. A. C. Blas, R. G. Carvajal, and J. R.- Angulo, “Enhanced single-stage folded cascode OTA suitable for large capacitive loads,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 65, no. 4, pp. 441–445, 2018.
[19] M. Garde, A. Lopez-Martin, R.G.Carvajal, and J.Ramirez-Angulo, “Super class AB recycling folded cascode OTA,” IEEE Journal of Solid–State Circuits, vol. 53, no. 22, pp. 2614–2623, 2018.
[20] A. Paul, J. R.-Angulo, A. D. Sanchez, A. J. L.-Martin, R. G. Carvajal, and F. X. Li, “Super-gain-boosted AB-AB fully differential miller Op-Amp with 156dB open loop gain and 174MV/V MHz pF/µW figure of merit in 130nm CMOS technology,” IEEE Access, vol. 9, pp. 57603–57617, 2021.
[21] J. B.-Legarra, C. A. C.-Blas, A. J. L.-Martin, and J. R.-Angulo, “Gain-boosted super class AB OTA based on nested local feedback,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 68, no. 9, pp. 3562–3573, 2021.
[22] D. Kahng and S. Sze, “A floating-gate and its application to memory devices,” Bell System Technical Journal, vol. 46, no. 4, pp. 1288–1295, 1967.
[23] Y. Ma, T. G. Gilliland, B. Wang, R. Paulsen, C.-H. W. A. Pesavento, H. Nguyen, T. Humes, and C. Diorio, “Reliability of pfet eeprom with 70-å tunnel oxide manu factured in generic logic cmos processes,” IEEE Transactions on Device and Mate rials Reliability, vol. 4, no. 3, pp. 353–358, 2004.
[24] S. Kinoshita, T. Morie, M. Nagata, and A. Iwata, “A pwm analog memory pro gramming circuit for floating-gate mosfets with 75- us programming time and 11 bit updating resolution,” IEEE Journal of Solid–State Circuits, vol. 36, no. 8, pp. 1286– 1290, 2001.
[25] Y. Wong, M. Cohen, and P. Abshire, “A floating-gate comparator with automatic offset adaptation for 10-bit data conversion,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 52, no. 7, pp. 1316–1326, 2005.
[26] C. Huang, P. Sarkar, and S. Chakrabartty, “Rail-to-rail, linear hot-electron injection programming of floating-gate voltage bias generators at 13-bit resolution,” IEEE Journal of Solid–State Circuits, vol. 46, no. 11, pp. 2685–2692, 2011.
[27] P. D. Smith, M. Kucic, and P. Hasler, “Accurate programming of analog floating-gate arrays,” IEEE Proceedings of the International Symposium on Circuits and Systems, 2002.
[28] G. Serrano, “Automatic rapid programming of large arrays of floating-gate ele ments,” IEEE Proceedings of the International Symposium on Circuits and Systems, 2002.
[29] A. Bandyopadhyay, G. Serrano, and P. Hasler, “Adaptive algorithm using hot electron injection for programming analog computational memory elements within 0.2Circuits, vol. 41, no. 9, pp. 2107–2114, 2006.
[30] A. Basu and P. E. Hasler, “A fully integrated architecture for fast and accurate pro gramming of floating gates over six decades of current,” IEEE Transactions on Very Large Scale Integration Systems, vol. 19, no. 6, pp. 953–962, 2011.
[31] J. F. Dickson, “On-chip high-voltage generation in mnos integrated circuits using an improved voltage multiplier technique,” IEEE Journal of Solid–State Circuits, vol. 11, no. 3, pp. 374–378, 1976.
[32] C. Huang, P. Sarkar, and S. Chakrabartty, “Rail-to-rail, linear hot-electron injection programming of floating-gate voltage bias generators at 13-bit resolution,” IEEE Journal of Solid–State Circuits, vol. 46, no. 11, pp. 2685–2692, 2011.
[33] J. Lu and J. Holleman, “A floating-gate analog memory with bidirectional sigmoid updates in a standard digital process,” IEEE Proceedings of the International Sym posium on Circuits and Systems, pp. 1600–1603, 2013.