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研究生: 廖彥祺
Yan-Qi Liao
論文名稱: 一種抑制3D TLC快閃記憶體之橫向電荷遷移的編碼策略
A Coding Strategy to Suppress Lateral Charge Migration for 3D TLC NAND Flash Memory
指導教授: 吳晋賢
Chin-Hsien Wu
口試委員: 吳晋賢
Chin-Hsien Wu
陳雅淑
Ya-Shu Chen
修丕承
Pi-Cheng Hsiu
張立平
Li-Pin Chang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2022
畢業學年度: 110
語文別: 英文
論文頁數: 38
中文關鍵詞: 3D TLC快閃記憶體可靠性保留錯誤橫向電荷遷移錯誤
外文關鍵詞: 3D TLC, NAND Flash Memory, Reliability, Retention Error, Lateral Charge Migration Error
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  • 如今,3D TLC快閃記憶體以其高容量和低成本成為了主流存儲介質。
    但是,3D TLC快閃記憶體存在一些可靠性問題,例如保留錯誤和讀取乾擾錯誤,
    這些問題可能會隨著時間的推移而累積並超過ECC(糾錯碼)的除錯量。
    特別是3D TLC快閃記憶體在早期使用階段,其P/E週期較低,但由於橫向電荷遷移,可能會嚴重遭受保留錯誤影響。
    在本文中,我們將提出一種編碼策略,以抑制橫向電荷遷移並減少3D TLC快閃記憶體處於低P/E週期時的保留錯誤。
    根據實驗結果,我們可以證明,與以前的方法相比,所提出的編碼策略可以更有效地減少保留錯誤。


    Nowadays, 3D TLC NAND flash memory has become the mainstream storage medium because of its high capacity and low cost. However, 3D TLC NAND flash memory has some reliability issues such as retention errors and read disturb errors that may accumulate over time and exceed the ECC (Error Correction Code) capacity. In particular, when 3D TLC NAND flash memory is in the early use stage, it has low P/E cycles but could seriously suffer the retention errors due to the lateral charge migration. In the paper, we will propose a coding strategy to suppress the lateral charge migration and also reduce the retention errors when 3D TLC NAND flash memory is in low P/E cycles. According to the experimental results, we can show that the proposed coding strategy can effectively reduce the retention errors when compared to the previous methods.

    Abstract Content Figure Directory Table Directory 1 Introduction 2 Background Knowledge 2.1 TLC NAND Flash Memory 2.2 Retention Errors 3 Related Work 3.1 Error Mitigation 4 Motivation 5 A Coding Strategy to Suppress Lateral Charge Migration 5.1 System Architecture 5.2 Coding Concept 5.2.1 Encoding Process 5.2.2 Weight Design 5.2.3 Relationship between BER Distributions and Weight Design 5.3 An Enhancement Skill 6 Performance Evaluation 6.1 Experimental Data 6.2 Distribution Count of a 7-state-gap Pair, 6-state-gap Pairs and 5-state-gap Pairs 6.3 Retention BER 7 Conclusion

    [1] Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo, and O. Mutlu, “Error
    characterization, mitigation, and recovery in flash-memory-based solid-
    state drives,” Proceedings of the IEEE, vol. 105, no. 9, pp. 1666–1704,
    2017.
    [2] K. Mizoguchi, T. Takahashi, S. Aritome, and K. Takeuchi, “Data-
    retention characteristics comparison of 2d and 3d tlc nand flash memo-
    ries,” in 2017 IEEE International Memory Workshop (IMW), 2017, pp.
    1–4.
    [3] Y. Kong, M. Zhang, X. Zhan, R. Cao, and J. Chen, “Retention correlated
    read disturb errors in 3-d charge trap nand flash memory: Observations,
    analysis, and solutions,” IEEE Transactions on Computer-Aided Design
    of Integrated Circuits and Systems, vol. 39, no. 11, pp. 4042–4051, 2020.
    [4] Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch, and O. Mutlu, “Improving
    3d nand flash memory lifetime by tolerating early retention loss and
    process variation,” Proc. ACM Meas. Anal. Comput. Syst., vol. 2, no. 3,
    dec 2018. [Online]. Available: https://doi.org/10.1145/3224432
    [5] H. Aihara, K. Maeda, S. Suzuki, and K. Takeuchi, “Extremely biased
    error correction method to reduce read disturb errors of 3d-tlc nand flash
    memories by 601–4.
    [6] Y. Cai, Y. Luo, S. Ghose, and O. Mutlu, “Read disturb errors in mlc nand
    flash memory: Characterization, mitigation, and recovery,” in 2015 45th
    Annual IEEE/IFIP International Conference on Dependable Systems and
    Networks, 2015, pp. 438–449.
    [7] K.-K. Yong and L.-P. Chang, “Error diluting: Exploiting 3-d nand
    flash process variation for efficient read on ldpc-based ssds,” IEEE
    Transactions on Computer-Aided Design of Integrated Circuits and
    Systems, vol. 39, no. 11, pp. 3467–3478, 2020.
    [8] A. Maconi, A. Arreghini, C. M. Compagnoni, G. Van den bosch, A. S.
    Spinelli, J. Van Houdt, and A. L. Lacaita, “Impact of lateral charge
    migration on the retention performance of planar and 3d sonos devices,”
    in 2011 Proceedings of the European Solid-State Device Research
    Conference (ESSDERC), 2011, pp. 195–198.
    [9] K. Mizoguchi, S. Kotaki, Y. Deguchi, and K. Takeuchi, “Lateral charge
    migration suppression of 3d-nand flash by vth nearing for near data
    computing,” in 2017 IEEE International Electron Devices Meeting
    (IEDM), 2017, pp. 19.2.1–19.2.4.
    [10] S. Suzuki, Y. Deguchi, T. Nakamura, and K. Takeuchi, “Endurance-
    based dynamic vthdistribution shaping of 3d-tlc nand flash memories to
    suppress both lateral charge migration and vertical charge de-trap and
    increase data-retention time by 2.7x,” in 2018 48th European Solid-State
    Device Research Conference (ESSDERC), 2018, pp. 150–153.
    [11] Y. Deguchi and K. Takeuchi, “Word-line batch vth modulation of tlc
    nand flash memories for both write-hot and cold data,” in 2017 IEEE
    Asian Solid-State Circuits Conference (A-SSCC), 2017, pp. 161–164.
    [12] T. Lehtonen, D. Wolpert, P. Liljeberg, J. Plosila, and P. Ampadu,
    “Self-adaptive system for addressing permanent errors in on-chip inter-
    connects,” IEEE Transactions on Very Large Scale Integration (VLSI)
    Systems, vol. 18, no. 4, pp. 527–540, 2010.
    [13] H. Choi, W. Liu, and W. Sung, “Vlsi implementation of bch error
    correction for multilevel cell nand flash memory,” IEEE Transactions
    on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 5, pp.
    843–847, 2010.
    [14] Q. Li, L. Shi, C. J. Xue, K. Wu, C. Ji, Q. Zhuge, and
    E. H.-M. Sha, “Access characteristic guided read and write cost
    regulation for performance improvement on flash memory,” in 14th
    USENIX Conference on File and Storage Technologies (FAST 16).
    Santa Clara, CA: USENIX Association, Feb. 2016, pp. 125–132.
    [Online]. Available: https://www.usenix.org/conference/fast16/technical-
    sessions/presentation/li- qiao
    [15] T. Tokutomi, S. Tanakamaru, T. O. Iwasaki, and K. Takeuchi, “Advanced
    error prediction ldpc for high-speed reliable tlc nand-based ssds,” in 2014
    IEEE 6th International Memory Workshop (IMW), 2014, pp. 1–4.
    [16] M. Zhao, J. Li, Z. Cai, J. Liao, and Y. Shi, “Block attribute-aware
    data reallocation to alleviate read disturb in ssds,” in 2021 Design,
    Automation Test in Europe Conference Exhibition (DATE), 2021, pp.
    1096–1099.
    [17] A. Grossi, L. Zuolo, F. Restuccia, C. Zambelli, and P. Olivo, “Quality-of-
    service implications of enhanced program algorithms for charge-trapping
    nand in future solid-state drives,” IEEE Transactions on Device and
    Materials Reliability, vol. 15, pp. 363–369, 06 2015.
    [18] S. Tanakamaru, C. Hung, and K. Takeuchi, “Highly reliable and low
    power ssd using asymmetric coding and stripe bitline-pattern elimination
    programming,” IEEE Journal of Solid-State Circuits, vol. 47, no. 1, pp.
    85–96, 2012.
    [19] K. Maeda, K. Mizoguchi, and K. Takeuchi, “Less reliable page error
    reduction for 3d-tlc nand flash memories with data overhead reduction by
    40data-retention time increase by 5.0x,” in 2019 Silicon Nanoelectronics
    Workshop (SNW), 2019, pp. 1–2.
    [20] Y. Cai, S. Ghose, Y. Luo, K. Mai, O. Mutlu, and E. F. Haratsch,
    “Vulnerabilities in mlc nand flash memory programming: Experimental
    analysis, exploits, and mitigation techniques,” in 2017 IEEE Interna-
    tional Symposium on High Performance Computer Architecture (HPCA),
    2017, pp. 49–60.
    [21] J. Cha and S. Kang, “Data randomization scheme for endurance enhance-
    ment and interference mitigation of multilevel flash memory devices,”
    ETRI Journal, vol. 35, no. 1, pp. 166–169, 2013. [Online]. Available:
    https://onlinelibrary.wiley.com/doi/abs/10.4218/etrij.13.0212.0273
    [22] Y. Deguchi, T. Nakamura, A. Hayakawa, and K. Takeuchi, “3-d nand
    flash value-aware ssd: Error-tolerant ssd without eccs for image recog-
    nition,” IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1800–
    1811, 2019.
    [23] Gerry, “180 bird species,” Mar 2020. [Online]. Available:
    https://www.kaggle.com/gpiosenka/100-bird-species
    [24] R. Tatman, “Speech accent archive,” Nov 2017. [Online]. Available:
    https://www.kaggle.com/rtatman/speech-accent-archive
    [25] M. Elesawy, “Real life violence situations dataset,” Apr 2019. [Online].
    Available: https://www.kaggle.com/mohamedmustafa/real-life-violence-
    situations-dataset
    [26] R. Garrard, “U.s. education datasets: Unification project,” Apr
    2020. [Online]. Available: https://www.kaggle.com/noriuk/us-education-
    datasets-unification-project
    [27] T. Bozsolik, “Data science cheat sheets,” Feb 2020. [Online]. Available:
    https://www.kaggle.com/timoboz/data-science-cheat-sheets

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