研究生: |
黃伯庭 Bo-ting Huang |
---|---|
論文名稱: |
蔽蔭遮罩圖案畫製作多晶矽薄膜電晶體反相器 Fabrication of Poly-Si TFT CMOS Inverter by Shadow Mask Patterning Process |
指導教授: |
葉文昌
Wen-chang Yeh |
口試委員: |
黃鶯聲
none 張勝良 none |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2009 |
畢業學年度: | 97 |
語文別: | 中文 |
論文頁數: | 60 |
中文關鍵詞: | 多晶矽薄膜電晶體 、蔽蔭遮罩 、互補式金氧半場效電晶體 |
外文關鍵詞: | thin film transistor, inverter, shadow mask |
相關次數: | 點閱:214 下載:1 |
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本研究成功以蔽蔭遮罩圖案化製程製作多晶矽薄膜電晶體和多晶矽反相器,所製作的p型與n型薄膜電晶體其通道長和寬分別為30和80 μm,載子移動率分別為12.19和6.5 cm2/V-s,ION/IOFF電流比分別為6.23×105和4.23×105,臨限電壓分別為-16和6.4V,次臨界擺幅分別為1.2和2.4 V/decade,而多晶矽反相器動態特性為當Vdd和Vss分別為15和0V,其上升時間與下降時間分別為0.79 ms和0.81 ms。
In this research, we have successfully used shadow mask with all sputter–deposited process to fabricate polysilicon TFTs and polysilicon inverter on SiO2 substrate. The On/Off current ratio, mobility, subthreshold swing, threshold voltage of n-type TFTs are 4.23×105, 6.5cm2/V-sec, 2.4V/dec and 6.4V, respectively. And the parameters of p-type TFTs are 6.23×105, 12.19 cm2/V-sec, 1.2 V/dec and -16.4V, respectively. In polysilicon inverter, it was operated with 200Hz input pulses with a supply voltage Vdd of 15V, the rise time and fall time of output waveform of inverter was estimated to be 0.79 ms and 0.81 ms, respectively.
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