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研究生: 黃宏銘
Hong-Ming Huang
論文名稱: 5G NR LDPC解碼加速器其吞吐量感知排程之設計
Design of Throughput-Aware Scheduling for LDPC Decoding Accelerator Over 5G NR
指導教授: 徐勝均
Sendren Sheng-Dong Xu
口試委員: 許騰尹
Terng-Yin Hsu
柯正浩
Kevin Cheng-Hao Ko
徐勝均
Sendren Sheng-Dong Xu
學位類別: 碩士
Master
系所名稱: 工程學院 - 自動化及控制研究所
Graduate Institute of Automation and Control
論文出版年: 2023
畢業學年度: 111
語文別: 中文
論文頁數: 80
中文關鍵詞: 第五代行動通訊新無線軟體定義實體層低密度奇偶檢查碼解碼現場可程式化邏輯閘陣列排程
外文關鍵詞: The 5th Generation Mobile Networks (5G) New Radio (NR), Software-Defined Physical Layer, Low-Density Parity Check Code (LDPC), Decoding, Field Programmable Gate Array (FPGA), Scheduling
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  • 致謝 I 摘要 II Abstract IV 目錄 VI 圖目錄 VIII 表目錄 IX 第一章 緒論 1 1.1 研究背景與動機 1 1.2 研究目的 2 1.3 研究方法與貢獻 3 1.4 論文架構 3 第二章 預備知識 5 2.1 第五代行動通訊新無線介紹 5 2.1.1 第五代行動通訊新無線發展 5 2.1.2 三大使用情境 6 2.2 第三代合作夥伴計畫 9 2.3 傳統無線網路架構 12 2.4 開放式無線電存取網路 13 2.5 實體層介紹 14 2.6 實體層上行通道介紹 16 2.7 幀結構 18 2.8 OpenAirInterface平臺 21 2.9 多執行緒概論 24 2.10 低密度奇偶檢查碼 26 第三章 5G NR上行解碼之架構 29 3.1 問題陳述 29 3.2 原始程式架構分析 31 3.3 整合FPGA LDPC Decoder至上行流程 32 3.3.1 介面參數與資料處理流程 32 3.3.2 整合FPGA LDPC加速器之架構 33 3.4 平行程式設計架構 34 3.4.1 資料切片 35 3.4.2 任務分配 36 3.4.3 執行緒流程 36 3.5 多使用者的排程流程設計架構 38 3.5.1 氣泡排序法(Bubble Sort) 38 3.5.2 多使用者之排程器 38 第四章 測試結果與討論 41 4.1 評估標準 41 4.2 實驗流程 41 4.3 實驗結果與分析 44 4.3.1 原始架構時間 44 4.3.2 整合FPGA加速器時間測試 46 4.3.3 平行程式時間測試 47 4.3.4 多使用者之吞吐量測試 50 第五章 結論與未來展望 55 5.1 結論 55 5.2 未來展望 56 參考文獻 58

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