本篇論文提出了極化碼(Polar code)分佈連續消除位元翻轉(Segmented SC-Flip)解碼器之超大型積體電路(Very-large-scale integration，VLSI)硬體設計與實現，演算法以極化碼連續消除(Successive cancellation，SC)演算法為基礎，加入位元翻轉技術以及分佈技術提高解碼效能，並在硬體設計上採用新式的處理單元(Process element，PE)減少關鍵路徑(Critical path)與面積，並採用半平行化架構犧牲適當的解碼週期來減少處理單元數量，除此之外，還藉由提出的零節點去除單元移除不需要計算的節點提高吞吐率(Throughput)。
本篇論文使用MATLAB進行演算法之開發與模擬驗證，硬體實現則是使用Verilog在Xilinx Virtex-7 VC707開發版進行設計，並且將設計電路藉由TSMC 40nm CMOS製程技術進行晶片設計。

This paper proposes the very-large-scale integration(VLSI) hardware design and implementation of the polar code segmented successive cancellation flip decoder. The algorithm is based on the polar code Successive Cancellation(SC) algorithm and adds bit-flipping technology and segmented technology to improve the decoding performance. In the hardware design, the new process element is used to reduce the critical path and area, and the semi-parallel architecture is used to sacrifice an appropriate decoding cycle to reduce the number of process elements. In addition, the zero node removal unit proposed in this paper removes nodes that do not require computation to improve throughput.
This paper uses MATLAB for the development and simulation of the algorithm. The hardware implementation is designed by using Verilog on the Xilinx Virtex-7 VC707 Evaluation Kit, and the proposed Segmented SCF decoder is synthesized using Design Compiler and IC Compiler base on TSMC 40nm CMOS technology.

[1] E. Arikan, “Channel polarization: A method for constructing capacity-achieving codes,’’ 2008 IEEE International Symposium on Information Theory, Toronto, ON, 2008, pp. 1173-1177 Jul. 2008.
[2] E. Arikan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels,’’ IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051-3073, July 2009.
[3] P. Trifonov, “Efficient Design and Decoding of Polar Codes,’’ in IEEE Transactions on Communications, vol. 60, no. 11, pp. 3221-3227, November 2012.
[4] J. Dai, K. Niu, Z. Si, C. Dong, and J. Lin, “Does Gaussian Approximation Work Well for the Long-Length Polar Code Construction,” IEEE Access, 2017.
[5] R. Mori and T. Tanaka, “Performance of Polar Codes with the Construction using Density Evolution,’’ in IEEE Communications Letters, vol. 13, no. 7, pp. 519-521, July 2009
[6] I. Tal and A. Vardy, ‘‘How to Construct Polar Codes,’’ IEEE Trans. Inf. Theory, vol. 59, no. 10, pp. 6562–6582, Oct. 2013.
[7] 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; NR; Multiplexing and channel coding, Release 16, V16.8.0, 3GPP TS 38.212, Jan. 2022.
[8] H. Zhang et al., ‘‘Parity-Check Polar Coding for 5G and Beyond,’’ 2018 IEEE International Conference on Communications (ICC), Kansas City, MO, 2018, pp. 1-7, May 2018.
[9] C. Leroux, I. Tal, A. Vardy and W. J. Gross, ‘‘Hardware architectures for successive cancellation decoding of polar codes,’’ 2011 IEEE International Conf. on Acoustics, Speech and Signal Processing (ICASSP), pp. 1665-1668, May 2011
[10] M. P. C. Fossorier, M. Mihaljevic and H. Imai, ‘‘Reduced complexity iterative decoding of low-density parity check codes based on belief propagation,’’ IEEE Transactions on Communications, vol. 47, no. 5, pp. 673-680, May 1999
[11] Z. Zhang, K. Qin, L. Zhang, H. Zhang and G. T. Chen, ‘‘Progressive Bit-Flipping Decoding of Polar Codes over Layered Critical Sets’’, in Proc. IEEE Global Communications Conference (GLOBECOM), pp. 1-6, Dec. 2017.
[12] Z. Zhang, K. Qin, L. Zhang, and G. T. Chen, ‘‘Progressive Bit-Flipping Decoding of Polar Codes: A Critical-Set Based Tree Search Approach,’’ IEEE Access, vol. 6, pp. 57738–57750, 2018
[13] S. Li, Y. Deng, X. Gao, H. Li, L. Guo, and Z. Dong, “Generalized Segmented Bit-Flipping Scheme for Successive Cancellation Decoding of Polar Codes With Cyclic Redundancy Check,” IEEE Access, vol. 7, pp. 83424–83436, 2019.
[14] H. Zhou, C. Zhang, W. Song, S. Xu, and X. You, “Segmented CRC-Aided SC List Polar Decoding,” in Proc. IEEE 83rd Vehicular Technology Conference, May 2016, pp. 1–5.
[15] U. Lee, j. H. Roh, C. Hwangbo and M. H. Sunwoo, “A Uniformly Segmented SC-Flip Decoder for Polar Codes with Memory Reduction Methods,” 2021 IEEE International Symposium on Circuits and Systems (ISCAS), May 2021, pp. 1–5.
[16] C. Leroux, A. J. Raymond, G. Sarkis, and W. J. Gross, “A Semi-Parallel Successive-Cancellation Decoder for Polar Codes,” IEEE Transactions on Signal Processing, vol. 61, no. 2, 2013.
[17] C. Zhang, B. Yuan and K. K. Parhi, “Reduced-latency SC polar decoder architectures,” 2012 IEEE International Conference on Communications (ICC), Ottawa, ON, 2012, pp. 3471-3475, June 2012
[18] B. Yuan, K. K. Parhi, “Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 4, pp. 1241-1254, April 2014
[19] C. Cheng and K. Parhi, “High-speed parallel CRC implementation based on unfolding, pipelining, and retiming,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 10, pp. 1017–1021, 2006.
[20] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. Hoboken, NJ: Wiley, 1999.
[21] O. Afisiadis, A. Balatsoukas-Stimming and A. Burg, “A low complexity improved successive cancellation decoder for polar codes,” IEEE 48th Asilomar Conf. Signals, syst. comput., Nov. 2014, pp. 2116-2120.
[22] A. Mishra, A. J. Raymond, L. G. Amaru, G. Sarkis, C. Leroux, P. Meinerzhagen, A. Burg, and W. J. Gross, “A successive cancellation decoder ASIC for a 1024-bit polar code in 180 nm CMOS,” IEEE Asian Solid-State Circuits Conf. (A-SSCC), 2012, pp. 205–208.