盲訊號分離技術被廣泛使用於需要分離混合訊號的應用中，而獨立成分分析演算法為其中最有效的演算法。獨立成分分析演算法利用訊號間統計上的獨立性及非高斯性質有效分離混合獨立訊號源。然而獨立成分分析演算法的運算量非常龐大，因此造成極高的運算延遲以及積體電路複雜度。本論文提出自適應且低延遲的獨立成分分析演算法及處理器架構。具體而言，本文提出了一種基於動量梯度下降最佳化及自適應學習步長控制的獨立成分分析演算法，使得演算法的整體疊代次數得到巨大的改善，並且只有些許的分離效能損失。此外，為了以低延遲且低複雜度的方式來計算多種不同的分佈函數，本論文提出了預先估算分佈的技巧，並應用於處理器架構設計中。我們專門設計了硬體利用的處理流程及效率，能夠在使用最少硬體元件的狀況下將處理速度最大化。我們所提出的獨立成分分析處理器是基於數位積體電路設計流程以及FPGA平台開發流程設計與實現。在論文的實驗結果中表明，我們所提出的獨立成分分析處理器以約 256.76k 個邏輯閘的複雜度實現每秒 3.81k 個矩陣運算的處理速度。與先前文獻的設計相比，我們所提出的獨立成分分析處理器實現了最高的處理速度並且有最高的資源使用效率。

This thesis presents the algorithm and VLSI architecture design of an adaptive independent component analysis (ICA) processor that achieves high-throughput and low-complexity. A novel ICA algorithm is presented with the momentum gradient descent optimization and an adaptive control of step size scheme so that the number of iterations for the algorithm is significantly reduced. The performance degradation of the proposed algorithm is minimal. Furthermore, in order to perform the computation of multiple distribution functions with low-latency and low-complexity, a novel early-distribution-estimation scheme is employed in the designed ICA processor. The processing flow and the efficiency for the hardware utilization are specifically designed so that the processing speed is maximized with a minimum employment of hardware components. The proposed ICA processor is designed and implemented based on the ASIC flow as well as on the FPGA. The evaluations based on the post-layout estimation show that, the proposed processor achieves a throughput of 3.81k Matrices per second with a complexity of 256.76k gate entity. Comparing with prior works, the proposed ICA processor achieves lowest processing latency as well as best hardware efficiency.

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