由於快閃記憶體具有高效能、低功耗與較好的抗震能力等特點，它被廣泛使用在筆記型電腦、手機、固態硬碟等消費性電子產品上。快閃記憶體利用儲存在浮閘上的電子數量多寡來儲存資料，而隨著製程與技術的進步，快閃記憶體一個細胞能儲存的位元數越來越多，使其雜訊邊界縮小，導致隨著細胞抹寫次數 (P/E Cycle) 的上升，記憶體的可靠度與耐久度嚴重下降。最常被用來解決這個問題的方法為使用錯誤更正碼技術，錯誤更正碼能有效對付快閃記憶體主要的故障：永久性故障與干擾性故障，但快閃記憶體不支援相同位置資料更新 (In-Place Update)，因此編碼字內的故障數會隨時間累積，當一個編碼字內的故障數量超過其保護能力範圍時，該編碼字就無法被修復。
因此，本論文提出適應性錯誤容忍技術來解決這些問題，本技術主要的想法為在錯誤更正碼保護能力固定的情況下，我們提出修正餘度 (Correction Slack) 的概念，藉由計算錯誤更正碼剩餘修復能力的數量，只針對錯誤更正碼剩餘修正能力較低的編碼字，藉由記錄錯誤位置進行額外保護，並設定累積錯誤數已超過 ECC 保護能力的編碼字所在的頁為關鍵頁，對其進行定期的虛擬錯誤刷除，以防止故障累積超過其保護能力而無法被修復。
本研究實現了適應性錯誤容忍技術的硬體電路，並在一個128 MB 的快閃記憶體上分析了本方法的修復率、良率、可靠度以及硬體成本。根據實驗的結果，在配備 48 組 CAM 欄位、編碼字長度為 256 位元時，我們的修復率相較只使用錯誤更正碼提升達 32%，在較差的情況下良率也能維持在 93 % 以上，可靠度亦能在 106 小時後維持 91% 的水準，而所使用的硬體成本相較整個快閃記憶體只要0.12 % 以下。

Due to the inherent features of high performance, low power consumption and shock resistance, flash memories are widely used in consumer products such as notebooks, smart phones, SSDs, and so on. The data stored in a flash memory cell is determined by the number of charges programmed on its floating gate. Since the number of bits can be stored in a single cell keeps increasing continuously, the noise margin on each Vth level of the multiple-level cells shrinks significantly. This will then lead to reliability and endurance issues when the program and erase counts increase. To solve this problem, the most popularly used technique is error correction code (ECC). ECC can effectively conquer the main fault types of flash memories, including permanent faults and disturb faults. However flash memories don’t support in-place update. Therefore, we cannot correct the stored data within the flash memory cell. When the number of faulty bits in a codeword exceeds the ECC correction capacity, this codeword cannot be corrected successfully.
Therefore, this thesis proposes adaptive fault tolerant techniques to solve this problem. The main idea is to introduce the concept of correction slack, which means the remaining ECC correction capacity. Our techniques only protect the codeword with less correction slack by recording the error locations determined by the ECC decoding circuitry. If a page containing a codeword with correction slack less than or equal to 0, this page will be marked as a critical page. To prevent the accumulation of faulty bits and then cause fail repair, we also propose virtual scrubbing technique which scrubs faulty bits periodically.
The VLSI design of the proposed techniques and architectures are implemented. Moreover, the repair rate, yield, reliability, and hardware overhead of 128 MB flash memory are also analyzed. According to experimental results with 48 CAM entries and 256 bits per codeword, we can increase 32% of repair rate than merely using the conventional ECC technique. The yield can achieve up to 93% in the worst case. Furthermore, the reliability of a flash memory remains higher than 91% after 106 hours of normal operations. The hardware overhead for incorporating the proposed technique of a flash size flash memory is only 0.12%.

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