本論文實現一個無量測範圍限制，以一組鎖相迴路為基礎且具數位校準之時間至數位轉換器。時間至數位轉換器的功用就是將待測時間轉換為數位形式輸出，目前被廣泛應用於許多量測儀器與電路中。本研究團隊於2005年提出一個具自我校準之游標卡尺法時間至數位轉換器，藉由鎖相廻路具有自我校準之能力，成功去除溫度、電壓與製程之變異，使該架構在不同環境因素下能保有相同解析度，但經實際量測，當待測時間較長時，會造成可觀的累積誤差。本論文延續先前架構，由鎖相迴路直接提供粗測電路穩定的計數時脈訊號，並提出一個新式數位鎖相迴路，透過連續趨近暫存器校準數位鎖相迴路輸出頻率，產生較高頻率提供給細測電路，採用游標卡尺法計數。鎖相廻路和新式數位鎖相迴路分別鎖定兩組相近頻率即可完成待測時間的粗測與細測，使得本時間至數位轉換器在不同環境因素下也能保有相同之解析度。本電路實現於TSMC 2P4M 0.35um製程，晶片面積0.55mm2。操作頻率在10 MHz時，電路解析度為24.8ps，功率消耗50.4mW。

This paper proposes a time-to-digital converter (TDC) based on PLL which has digital calibration circuit and theoretically unlimited input range. The TDC is purposed to transform time interval into digital output and widely used in many instrumentation systems or equipments. Our research team was proposed a Vernier-based TDC in 2005. PLL is stabilized against process, voltage and temperature (PVT) variations by self-calibration. But when using the TDC in measuring long time period between two signals, there are many errors in this application. In order to improve these problems, we feed the reference clock of coarse counter from the voltage-controlled oscillator in PLL. A DPLL design using the new architecture is provided higher frequency to fine circuit. The DPLL architecture uses successive approximation register (SAR) to adjust its oscillation frequency. Since the proposed circuit utilizes PLL and DPLL for both coarse and fine measurements. It makes the excellent sensitivity reduction capability of the circuit. The proposed TDC has been implemented in 0.35um standard 2P4M CMOS technology and the chip size is 0.55mm2. In the 10MHz operation frequency, the TDC has 24.8ps timing resolution and power consumption is 50.4mW.

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