研究生: |
周郁桀 Yu-Jie Chou |
---|---|
論文名稱: |
應用於量子運算低雜訊次取樣鎖相迴路 Low Phase Noise Sub-sampling Phase-locked Loop for Quantum Computing |
指導教授: |
陳筱青
Hsiao-Chin Chen |
口試委員: |
姚嘉瑜
Chia-Yu Yao 邱弘緯 Hung-Wei Chiu |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2021 |
畢業學年度: | 109 |
語文別: | 英文 |
論文頁數: | 88 |
中文關鍵詞: | 量子電腦 、Ku頻段 、毫米波積體電路 、衛星通訊 、次取樣鎖相迴路 |
外文關鍵詞: | MMIC, statellite communication |
相關次數: | 點閱:393 下載:0 |
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本論文使用TSMC 90奈米CMOS技術實現應用於量子運算之單晶片低雜訊次取樣鎖相迴路,電壓控制振盪器的可操作頻率範圍為18.08 GHz到18.38GHz,相位雜訊在1 MHz的偏移頻率下為-104.7 dBc/Hz ~ -105.6 dBc/Hz, 此電路在頻帶內之相位雜訊在100 kHz的偏移頻率下為-93.5 dBc/Hz,頻帶外之相位雜訊在10 MHz的偏移頻率下約為 -123.5 dBc/Hz。在電路完成鎖定後,此時電路的功耗為68.4 mW;根據模擬結果,系統的鎖定時間約為3 μs,晶片面積為1.9mm2。
A 18.3 GHz sub-sampling PLL is implemented using TSMC 90-nm CMOS technology to generate microwave signal for quantum computers. The on-chip VCO achieves the tuning range from 18.08 GHz to 18.39 GHz, and exhibits the phase noise of -104.7 ~ -105.6 dBc/Hz at 1 MHz frequency offset, from the 18.08 GHz to 18.39 GHz carriers. Consuming the power of 64.8 mW and the chip area of 1.9 mm^2, the sub-sampling PLL delivers the 18.3 GHz signal with the in-band phase noise of -93.5 dBc/Hz and the out-band phase noise is -123.5 dBc/Hz at 10 MHz frequency offset. The locking time is 3 μs.
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