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研究生: 林嘉俊
Chia-Chun - Lin
論文名稱: 5.5GHz 快速鎖定全數位式鎖相迴路設計
5.5GHz Fast Lock All Digital PLL Design
指導教授: 姚嘉瑜
Chia-Yu Yao
口試委員: 陳筱青
Hsiao-Chin Chen
彭盛裕
Sheng-Yu Peng
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2017
畢業學年度: 105
語文別: 中文
論文頁數: 89
中文關鍵詞: 相位誤差補償頻率誤差補償數位控制振盪器全數位式鎖相迴路
外文關鍵詞: all-digital phase-locked loop, phase error compensation, frequency error compensation, digitally controlled oscillator
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本論文提出利用新型相位及頻率誤差補償演算法的全數位式鎖相迴路。首先,
我們提出了一個振盪週期對應控制碼呈高解析度的新型數位控制振盪器(DCO)
架構,DCO 採用一般常見LC-tank 架構來控制11-bit dco_code,可提供2048 個
不同的頻率,DCO 振盪頻率約為4.8935GHz-5.9836GHz。
相位誤差補償機制,是利用計數參考訊號Fref 正緣與經除頻器除頻之後產
生的回授訊號Fback 正緣間的數位控制振盪器週期數,藉此修正除頻器除數,以
抵銷Fref 和Fback 間的相差,先解決鎖相迴路追鎖頻率時的相位誤差累積問題,
而其後每個Fref 週期都同時進行頻率誤差與相位誤差補償的機制。
頻率誤差補償的機制是由相位誤差補償機制拓展出來,計數Fback 正緣和
Fref 正緣間的DCO 訊號週期差,以計算控制碼的改變量(ΔCode),達到校正頻率
的功能。
相位頻率誤差補償機制應用在全數位式鎖相迴路的追鎖過程。待系統鎖定後
再藉由拓展控制碼位元數,以增加鎖定後頻率的穩定性。
本論文的晶片是採用TSMC 0.18 um 1P6M CMOS 製程來實現,除了高解析
度的數位控制振盪器、除頻器、DTS 需要採用Full-custom 設計流程完成外,其
餘電路完全可由Cell-Based 設計流程來完成。DCO 操作頻段為5.48 GHz 至
5.62GHz,而其解析度在TT 27℃時介於0.0868ps ~ 0.0891 ps。系統操作功率
消耗為20.538mW 、晶片面積大約為1.965 mm2。


This thesis presents a phase-frequency error compensation mechanism for
an all digital phase-locked lopp(ADPLL). First a novel digital-controlled
oscillator(DCO) was designed. Eleven pairs of symmetrical PMOS varactors are
connected in parallel in the tank circuit. The DCO’s output frequency range is from
4.8935GHz-5.9636GHz.
The phase error compensation mechanism changes the divisor of the divider
to resolve the problem of phase error accumulation by calculating the cycle time
difference between the positive edge of the reference clock and the positive edge of
the feedback signal from the DCO. After that, The frequency error compensation
mechanism is activated to generate the correcting amount of the control-code to fix
the frequency error. Next, the phased-frequency error compensation mechanism is
used in the acquisition mode of the ADPLL. In the tracking mode, after the system is
locked, the control code is extended to enhance the frequency stability.
The proposed ADPLL chip was fabricated in TSMC 0.18um 1P6M CMOS
process. The DCO, Buffer and Divider was implemented by the full-custom design
flow. The other part of the ADPLL is realized by the cell-based design flow. The
DCO’s output frequency range is from 5.48 GHz to 5.62 GHz and its resolution is
between 0.0868 ps and 0.0891 ps at TT 27℃. The power consumption is 20.538
mW, and the chip size is around 1.965 mm2.

摘要 I Abstract II 誌謝 III 目錄 IV 圖目錄 VII 表目錄 XI 第一章 緒論 1 1-1 研究動機 1 1-2 論文規劃 4 第二章 鎖相迴路介紹與系統應用 5 2-1 類比式鎖相迴路 5 2-2 電荷幫浦式鎖相迴路 6 2-3 全數位式鎖相迴路 7 2-4 系統應用 9 第三章 具相位及頻率誤差補償之 數位式鎖相迴路系統架構介紹與模擬 12 3-1 系統架構 12 3-2 數位控制振盪器 16 3-2.1 數位控制振盪器架構 16 3-2.2 後模擬結果 18 3-3 Buffer 電路架構 28 3-4 CML除頻器 29 3-5 差動轉單端電路(DTS) 31 3-6 Pulse Swallow 除頻器電路 32 3-7 Count_N&L 、Count_K 37 3-8 相位頻率偵測器 40 3-9 相位頻率誤差補償器 42 3-9.1 相位誤差累積問題 43 3-9.2 相位誤差補償機制 44 3-9.3 頻率誤差補償機制 47 3-9.4 相位頻率誤差補償器電路架構 50 3-10 細調控制器 51 3-11 系統前模擬結果 55 3-12 系統合成後結果 58 第四章 晶片佈局與量測 60 4-1 設計流程 60 4-2 晶片佈局規劃 61 4-3 量測環境 62 4-4 量測結果 64 4-4.1 DCO 頻譜及相位雜訊之量測結果 65 4-4.2 鎖定過程控制碼之量測結果 68 4-4.3 量測結果討論 69 4-5 晶片規格列表與文獻比較 70 第五章 結論與未來展望 72 5-1 結論與未來展望 72 參 考 文 獻 73

[1] Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, and An-Yeu Wu, “A Two-Cycle Lock- In Time ADPLL Design Based on a Frequency Estimation Algorithm, ” IEEE Trans. Circuits Syst . I I : Exp. Briefs,vol . 57, no. 6, June 2010.
[2] T. Wat an ab e an d S . Yamau c h i , “An all -digi tal PLL for frequency multiplication by 4 to 1022 with seven - cycle lock time, ” IEEE J.Sol id-State Circuits, vol . 38, no. 2, pp. 198–204, Feb. 2003.
[3] D. Sheng, C. -C. Chung, C. -Y. Le e, “An Ul t r a -Low-Power and Portable Digi tally Control led Oscillator for SoC Applications , ” IEEE Trans. Circui ts Syst . II : Exp. Briefs, vol . 54, pp. 954 – 958,2007.
[4] P.-L. Chen, C. -C. Chung, and C. -Y. Le e , “A port able digitally control led oscillator using novel v a r act o r s , ” IEEE Trans. Circuits Syst . II : Exp.Briefs , vol . 52, pp. 233–237, May 2005.
[5] D. Sheng, C. -C. Chung, and C. -Y. Le e , “An all -digital phase- locked loop with high- r es o l u t i o n f o r S oC ap p l i c at i o n s , ” IEEE VLSI D.A.T. ,
pp. 207–210, Apr. 2006
[6] Hua Geng, Dewei Xu, and Bin Wu, “A Novel Hardware-Based All -Digi tal Phase-Locked Loop Applied to Gr id-Connected Power Converters, ” IEEE Trans. on Industrial Electronics , vol . 58, no. 5, May 2011.
[7] Kuan-Chung Lu, Fu-Kang Wang, Tzyy- S h en g Ho r n g , “Ultralow Phase Noise and Wideband CMOS VCO Using Symmetr ical Body- Bi as PMOS Va r a ct o r s . ” IE E E Mi c r ow. Wireless Comp o n . Le t t . , vol . 23, no. 2, Feb. 2013.
[8] U. S i n g h an d M. M. Gr e en , “High - frequency CML clock dividers in 0.13-μm CMOS o p e r at i n g u p t o 3 8 GHz , ” IE E E J . S o l i d -State Circuits, vol . 40, no. 8, pp. 1658-1661, Aug. 2005.74
[9] J . G. Man ea t i s , “ L ow -jitter process -independent DLL and PLL based on self - b i as e d t e ch n i q u es , ” IEEE J . Solid -State Circuits, vol .
31, pp. 1723-1732, Nov. 1996.
[10] J . Yu a n an d C. S v e n s s o n , “Hi g h -speed CMOS circuit t e ch n i q u e, ”IEEE J. Sol id-State Circuits, vol . 24, pp. 62-70, Feb. 1998.
[11]K .-H. Choi , J. -B. Shin, J. -Y. Sim, and H. -J . P ar d , “An i n t e r p o l at i o n digitally control led oscillator for a wide - range all -digital P L L, ”IEEE Trans.Circuits Syst . I, Reg. Papers , vol . 56, no. 9, pp.2055–2063, Sep. 2009.
[12]廖煥森, Low-Power Phase-Locked Loop Design. M.S. Thesis,Tamkung Universi t y, 1999
[13]C.-C. Cheng, The analysis and design of all digital phase - locked loop(ADPLL) . National Chiao-Tung University, M.S. Thesis, 2001.
[14]Yuanfeng Sun, Xueyi Yu, Woogeun Rhee, Dawn Wang, and Zhihua Wang, “A Fast Set t l i n g Dual -Path Fractional -N PLL With Hybrid-Mo d e Dynamic Band width Control , ” IEEE Microw.Wireless Compon. Let t . , vol . 20, no. 8, Aug. 2010.
[15]Kyoungho Woo, Yong Liu, Eunsoo Nam, and Donhee Ham,
“ Fa s t -Lock Hybr id PLL Combining Fractional -N and Integer-N Modes of Di ff e r i n g Band widths , ” IEEE J. Solid -State Circuits, vol .43, no. 2, Feb. 2008.
[16]Tsung-Hsien Lin, Ching-Lung Ti , and Yao-Ho n g Li u , “Dynamic Current -Matching Charge Pump and Gated-Offset Linearization Technique for Del ta-Sigma Fractional -N P L Ls , ” IEEE Trans .Circuits Syst . I, Reg. Papers, vol . 56, no. 5, May 2009.
[17]Marzo Zanuso, Salvatore Levant ino, CarloSamor i , and Andrea L.Lacaita, “A Wideband 3.6GHz Digital ΔΣ Fr actional -N PLL With Phase Interpolation Divider an d Digital S p u r C an cell at i o n , ” IE E E J .Sol id-State Circuits, vol . 46, no. 3, Mar. 2011.
[18]Heng-Yu Jian, Zhiwei Xu, Yi -Cheng Wu, and Mau-Chung Frank Chang , “A Fractional -N PLL for Multiband(0.8-6GHz)Communications Using Binary-Weighted D/A Differentiator and 75 Offset - Frequency Δ - Σ Mo d u l at o r, ” IEEE J . S o l i d -State Circuits, vol.
45, no. 4, Apr. 2010.
[19]Christ ian Venerus, Ian Gal ton, ” A TDC -Free Most ly-DigitalFDC-PLL Frequency Synthesizer With a 2.8– 3 . 5 GHz DCO” IEEE Journal of sol id-state circui t ,vol 50, no2,February 2015.
[20]Mohammad Hekmat , Farshid Aryanfar, Jason Wei , Vi jay Gadde,and Reza Navid, ” A 2 5 GHz Fast -Lock Digital LC PLL With Multi phase Output Using a Magnetically-Coupled Loop of Oscillators ” IEEE Journal of sol id-state circui t ,vol 50, no2,February 2015.
[21]Sigang Ryu, Hwanseok Yeo , Yoontaek Lee, Seuk Son, Jaeha Kim, A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function ” IEEE Journal of sol id-state circuit ,vol 49, no8,August 2014
[22]Kinget P. , Integrated GHz voltage control led oscil lators, Kluwer Acdemic Publishers, New York, 1999.
[23]曾福祥, 具新型相位及頻率補償之全數位式鎖相迴路, 碩士論文,
國立台灣科技大學, 2014.
[24]劉深淵, 楊清淵, 鎖相迴路. 滄海書局, 2006.
[25]饒敬國, IEEE 802.11a 技術文件內容簡介, 暨南大學電機工程研
究所

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