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研究生: 施品丞
Pin-Chen Shih
論文名稱: 單電感雙輸出之三階降壓式轉換器
Single Inductor Dual Output Three Level Buck Converter
指導教授: 邱煌仁
Huang-Jen Chiu
林景源
Jing-Yuan Lin
口試委員: 邱煌仁
Huang-Jen Chiu
林景源
Jing-Yuan Lin
黃仁宏
Peter Huang
張佑丞
Yu-Chen Chang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 中文
論文頁數: 67
中文關鍵詞: 單電感雙輸出架構三階降壓式轉換器波谷電流模式控制
外文關鍵詞: Single inductor dual output (SIDO), Three level buck converter, Valley current mode control
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隨著在系統單晶片(System on Chip, SoC)手持式裝置的發展,電源轉換器希望利用更先進的製程已達到更小的佔位面積和更低的成本,並同時輸出多個電壓以滿足不同的元件需求。本論文提出的單電感雙輸出三階降壓式轉換器結合單電感雙輸出架構和三階降壓架構的優點,並使用波谷電流模式和電壓模式控制,在使用單一電感供給不同輸出的情況下,進一步降低所需之電感大小,滿足減小電感佔位面積的目的。
本晶片以TSMC 0.35 μm 2P4M CMOS 製程實現,晶片面積含PADs為3.4×1.65 mm2。功率級輸入電壓為 5 V、輸出電壓分別為1.5 V、1.2 V,切換頻率為200 kHz,外接電感與電容分別為33 μH與300 μF,功率開關使用外接元件,輸出負載範圍為300 mA至900 mA。


With the development of system-on-chip (SoC, system-on-chip) handheld devices, power converters would want to achieve smaller footprints and lower costs with new advanced IC processes. They also expect to be able to supply multiple sets of outputs at the same time. Single inductor dual output three level buck converter is proposed in this thesis. Using Valley current mode and Voltage mode control. It combines the advantages of single inductor dual output and three level buck architectures to achieve dual output with a single small inductor.
The chip is implemented with TSMC 0.35 μm 2P4M CMOS technology and the size of chip including pads was 3.4×1.65 mm2. The power stage input voltage is 5 V. The output voltages are 1.5 V and 1.2 V, and the switching frequency is 200 kHz. The off chip inductance and capacitance are 33 μH and 300 μF. The power switches are off chip. The output load range is 300 mA to 900 mA.

摘 要 ABSTRACT 誌 謝 目 錄 圖目錄 表目錄 第一章 緒論 1.1研究動機與目的 1.2論文大綱 第二章 三階降壓式轉換器架構與控制方法 2.1三階降壓式轉換器簡介 2.2三階降壓式轉換器工作原理 2.3三階降壓式轉換器控制模式 2.4二階與三階降壓式轉換器所需電感比較 第三章 單電感雙輸出電路架構與控制方法 3.1單電感雙輸出降壓式轉換器簡介 3.2單電感雙輸出降壓式轉換器工作原理 3.3 單電感雙輸出降壓式轉換器控制模式 第四章 單電感雙輸出三階降壓式轉換器 4.1 電路簡介 4.2 電路動作分析 4.3迴授控制 4.4補償器 第五章 轉換器設計與實現 5.1轉換器電路實現 5.2子電路設計 5.2.1同步鋸齒波產生器 5.2.2電感電流偵測之電路 5.2.3訊號錯相器之電路 5.2.4減法器之電路 5.3電路波德圖 第六章 模擬結果 6.1 三階單電感雙輸出降壓式轉換器之模擬波形 6.2 模擬結果比較與說明 第七章 晶片量測結果 7.1 晶片佈局圖 7.2 使用之外接元件 7.3 晶片腳位配置與定義 7.4 晶片量測波形 7.5 晶片量測結果 第八章 結論與未來展望 8.1結論 8.2未來展望 參考文獻

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