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研究生： 韓瑞誠
Jui-Cheng Han
論文名稱： 注入鎖定除頻器與四相位電壓控制振盪器之設計
Design of Injection Locked Frequency Dividers and Quadrature Voltage Controlled Oscillator
指導教授： 張勝良
Sheng-Lyang Jang
口試委員: 黃忠偉
Jong-Woei Whang
黃進芳
Jhin-Fang Huang
馮武雄
Wu-Shiung Feng
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 148
中文關鍵詞： 壓控振盪器 、鎖相迴路 、主動電感 、除頻器
外文關鍵詞： VCO, PLL, TAI, ILFD
相關次數： 點閱：328  下載：7 
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    • 本論文主要描述四個不同型式的振盪器與除頻器，其分別為“注入鎖定除頻器使用主動電感負載”、“5GHz低相位雜訊四相位哈特萊壓控振盪器”、”注入鎖定除頻器使用差動型式考畢茲振盪器”及”L-C共振腔注入鎖定除3電路”。前兩電路皆採用台積電所提供之零點一八微米互補式金氧半製程所製造，後兩電路皆採用台積電所提供之零點三五微米互補式金氧半製程所製造。
    主動電感負載電路因為沒有被動電感所以非常節省晶片面積，且可調範圍與注入鎖定範圍皆可超出已往的L-C振盪器，在電源1.8V量測到頻率可調範圍從1.46GHz到2.7GHz，注入功率大小為-4dBm的訊號時鎖定範圍高達3.4GHz(79%)，從2.6GHz到6GHz，功率消耗7.2mW，晶片面積為0.383*0.379mm2.
    低相位雜訊的5GHz四相位哈特萊壓控振盪器使用並聯訊號耦合與變壓器耦合來達成四相位機制，在電源1.8V量測到中心頻率為5.06GHz，輸出之相位雜訊在距離5.06GHz載波頻率1MHz處所量測之結果可達-125.6dBc/Hz，功率消耗17.4mW，FOM可高達-188.0dBc/Hz，晶片面積為0.982*0.992 mm2.
    注入鎖定除頻器使用差動型式考畢茲振盪器主要振電路使用兩個單端的PMOS考畢茲振盪器，將其電流源接成耦合型式產生差動訊號，注入鎖定電路使用單一顆NMOS接在差動輸出的兩端，在電源電壓3V情況量測下，可調頻率從3.48 GHz到3.86 GHz，注入功率大小為-3dBm的訊號時鎖定範圍有0.38GHz(10.3%)從6.75GHz到8GHz，功率消耗18mW，晶片面積0.74x0.52 mm2.

    This thesis presents an injection locked frequency divider (ILFD) employing tunable active inductors for the LC-tanks. The aim of using tunable active inductor is to extend the locking range and scaling down chip size. The CMOS ILFD consists of LC tank voltage-controlled oscillators (VCOs) with cross-coupled switching pair and was fabricated in the 0.18-um 1P6M CMOS technology. The divide-by-2 LC-tank ILFD is performed by adding an injection nMOS between the differential outputs of the divider. Measurement results show that at the supply voltage of 1.8V, the divider free-running frequency is tunable from 1.46 GHz to 2.7 GHz, and at the incident power of -4 dBm the locking range is about 3.4 GHz (79%), from the incident frequency 2.6GHz to 6.0GHz. The core power consumption is 7.2mW and the die area is 0.383*0.379 mm2.
    A novel low phase noise quadrature voltage controlled oscillator (QVCO) with two coupled Hartley VCOs is proposed and implemented using the standard TSMC 0.18um CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.8V supply voltage, the output phase noise of the QVCO is -125.6dBc/Hz at 1MHz offset frequency from the carrier frequency of 5.06GHz, and the figure of merit is -188.0dBc/Hz. At the supply voltage of 1.8V, the total power consumption is 17.4mW. The die area is 0.982 x0.992 mm2.
    A novel divide by 2 frequency divider (FD) fabricated in the TSMC 0.35um 2P4M CMOS technology is reported. The FD consists of two single-ended pMOS core Colpitts oscillators coupled with a cross-coupled nMOS pair to generate differential signals. The divide-by-2 LC-tank injection locked frequency divider uses only one injection nMOS with its drain and source connected to the differential outputs of the divider. The measurement results show that at the supply voltage of 3.0V, the divider free-running frequency is tunable from 3.48 GHz to 3.86 GHz, and at the incident power of -3 dBm the locking range is about 0.38 GHz (10.3%), from the incident frequency 6.75GHz to 8.0GHz. The core power consumption is 18mW. The die area is 0.74 x 0.52 mm2.
    In this thesis we study the operation principle of CMOS divide-by-3 injection locked frequency dividers (ILFDs). The ILFDs can provide differential outputs and are made of an LC-tank resonator with cross-coupled switching pairs, which are stacked in series with two injection MOSFETs. A mathematical formula is proposed to explain qualitatively the circuit operation principle and provide circuit design insights. Under large injection strength, the characteristics of the ILFD show the effect of the 2nd order nonlinearity of input transconductors. A divide-by-3 LC tank ILFD fabricated in the TSMC 0.35um CMOS 2P4M CMOS technology is used to support the design insights of mathematical model.

    中文摘要 1 Abstract 3 誌謝 5 Table of Contents 6 List of Figures 9 List of Tables 13 Chapter 1. Introduction 14 1.1 BACKGROUND 14 1.2 THESIS ORGANIZATION 16 Chapter 2. Overviews of Voltage-Controlled Oscillators 18 2.1 INTRODUCTION 18 2.2 THE OSCILLATOR THEORY [1] 19 2.3 SORTS OF OSCILLATORS 23 2.3.1 RESONATORLESS OSCILLATORS 23 2.3.2 LC-TANK OSCILLATORS 26 2.4 DESIGN CONCEPTS OF VOLTAGE-CONTROLLED OSCILLATORS 28 2.4.1 VCO CHARACTERISTIC PARAMETERS 29 2.5 PARALLEL RLC TANK [6] 37 2.5.1 QUALITY FACTOR [6] 38 2.5.2 INDUCTOR AND TRANSFORMER 41 2.5.3 CAPACITORS AND VARACTORS 59 2.5.4 RESISTORS 67 Chapter 3. ILFD With Tunable Active Inductor Load 69 3.1 INTRODUCTION 69 3.2 THE TUNABLE ACTIVE RESISTOR 70 3.3 THE ACTIVE INDUCTOR 73 3.4 THE TUNABLE ACTIVE INDUCTOR 78 3.5 INJECTION LOCKED FREQUENCY DIVIDER 81 3.5.1 Principle Of Injection Locked Frequency Divider 82 3.5.2 Locking Range 84 3.5.3 Switch ILFD 86 3.6 INJECTION LOCKED FREQUENCY DIVIDER WITH TAI 87 Chapter 4. A Novel Hartley Quadrature VCO 92 4.1 INTRODUCTION 92 4.2 TRADITIONAL QVCO CIRCUIT DESIGN 93 4.3 TRADITIONAL QUADRATURE CMOS VCO DESIGN 95 4.4 HARTLEY QUADRATURE CMOS VCO DESIGN 99 4.5 MEASUREMENT RESULTS 102 Chapter 5. Differential Colpitts Injection Locked Frequency Divider 106 5.1 INTRODUCTION 106 5.2 COLPITTS CIRCUIT DESIGN 107 5.3 MEASUREMENT AND DISCUSSION 110 Chapter 6. Divider-By-3 LC-Tank Injection Locked Frequency Divider 116 6.1 INTRODUCTION 116 6.2 CLASSICAL INJECTION-LOCKED CIRCUIT DESIGN 117 6.3 MEASUREMENT RESULTS 129 Chapter 7. Conclusion 142 References 145

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