由於NAND Flash Memory具有體積小、低耗電、非揮發性、快速儲存、高抗震等優點，成為目前廣泛使用的儲存裝置。為了降低成本與提高儲存容量，2D NAND Flash Memory從SLC逐漸發展至單位細胞密度較高的MLC及TLC，科技日新月異，製程技術逐漸往更低的奈米發展，但Flash Memory已經難以再降低小於20 nm的製程技術，這是因為每個快閃記憶體細胞的浮閘所保持的電子數量太低，導致無法有效的區分出電壓層級。因此，3D Flash Memory被提出成為目前較新的趨勢設計，3D Flash Memory在原本的2D平面透過多層的堆疊，細胞密度更高，使得成本降低及並增大儲存容量。但由於硬體架構的關係，將會導致嚴重的鄰近頁面寫入干擾問題，使得資料發生難以校正的錯誤，且較高的細胞密度可能造成大區塊問題，導致資料回收時頁面複製過多而造成效能下降。為了解決寫入干擾及大區塊問題，本文提出有效提升空間使用率的高性能三維度NAND型快閃記憶體設計，透過重新轉換位址至不同通道的不相鄰頁面，達到在高速存取下仍能避免區塊內的寫入干擾，並有效提升3D Flash Memory的空間使用率。

NAND flash memory becomes the most widely used storage device because of its numerous unique characteristics: non-volatile, low power consumption, small size, shock resistance, and good I/O performance. To cost down and increase capacity, SLC flash memory is replaced by MLC and TLC flash memory gradually. With the development of science and technology, it is so hard for flash memory to scale down below 20nm technology because few of electrons can be kept in the floating gate of each cell, and it is also difficult to determine the level of voltage values in each cell efficiently and correctly. As a result, 3D flash memory is proposed as the newest designs. 3D flash memory is stacked by multiple layers composed of 2D flash memory, so it has larger capacity and lower cost than 2D flash memory. However, 3D flash memory suffers from a serious program disturbance problem because of its hardware architecture. When programming one page, it will lead to unrecoverable error that happens at nearby valid pages. In addition to program disturbance, 3D flash memory also has a big size physical block. When garbage collection is triggered to recycle a physical block, many valid pages in the physical block could be copied out and cause large overhead. In order to alleviate the influence of these problems, this thesis proposes an efficient space utilization design for high-performance 3D NAND flash memory to achieve efficient space utilization and high performance accesses.

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