由於快閃記憶體的製程進步以及成本降低，使得相關產品在市場普及化。逐漸地快閃記憶體產品轉以控制晶片的技術規格為導向，而錯誤更正碼的演算法為其中關鍵技術之一。BCH碼是運用在NAND型快閃記憶體的錯誤控制上傳統主流的演算法，然而面對新一代的NAND型快閃記憶體系統的高錯誤特性，工業界必須尋找更強大且有效率的錯誤更正碼來更正錯誤。而低密度奇偶檢查碼就是很好的選擇，尤其當使用軟性資訊來解碼時，更能達到高效能。
　　本論文主要是實現低密度奇偶檢查碼的解碼演算法硬體線路。於數種已知的低密度奇偶檢查碼的解碼演算法中我們選擇採用位元節點為中心之循序排程演算法來降低演算法的硬體複雜度。此演算法屬於一種分組曳步解碼的演算法，也就是結合並行與串列的解碼方式。使用此方式可以減少解碼疊代次數，而不會使效能損失。同時它可以降低線路的連線數以利繞線，在解碼器中的檢查節點單元與位元節點單元也可以有效的被簡化。最後我們使用UMC 0.11um SP製程，來合成我們所實現的電路。

　　With advances in the flash memory process technology and reduction of manufacturing costs, flash memory has been used in many popular products recently. The controller IC technology is the critical one making flash memory function well. Error control coding is one of the key components in the controller IC. BCH code has been adopted for the error control on the NAND flash memory for many years. However, due to high error characteristic of the new-generation NAND flash memory system, the industry must find more powerful and efficient error correction codes to perform error correction. Low-density parity-check codes (LDPC codes) are good candidates, especially, when soft information is used to decode. LDPC codes usually result in good bit error performance.
　　This thesis is mainly focus on implementing the hardware architecture of decoding algorithm for LDPC codes. After investigating several well-known decoding algorithms, the variable-node-centric sequential scheduling algorithm is adopted to reduce the hardware complexity of the decoder. This algorithm is one kind of group shuffled scheduling algorithms, which combine the parallel and serial decoding features to reduce the hardware complexity. By using this algorithm one can reduce the connection number of the hardware architecture to make routing easier. Moreover, the check node units and variable node units in the decoder can be simplified efficiently. The proposed LDPC decoder circuit is synthesized with UMC 0.11 μm standard process and the size of gate count is provided.

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