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研究生: 藍翊倫
Yi-Lun Lan
論文名稱: 基於TLC快閃記憶體之保留錯誤緩解的位元配對寫入方法
A Bit-Pair Write Position Selection for Retention-Error Mitigation on TLC NAND Flash Memory
指導教授: 吳晋賢
Chin-Hsien Wu
口試委員: 吳晋賢
Chin-Hsien Wu
陳雅淑
Ya-Shu Chen
謝仁偉
Jen-Wei Hsieh
張原豪
Yuan-Hao Chang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 中文
論文頁數: 50
中文關鍵詞: 快閃記憶體三階儲存單元可靠度保留錯誤
外文關鍵詞: NAND Flash, triple-level cell (TLC), Reliability, Retention Error
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  • 由於快閃記憶體具有有限的P/E cycles,因此超過快閃記憶體單位限制的P/E cycles後會出現嚴重的可靠性問題,主要原因是快閃記憶體單元中的寫穿(wear-out)現象,受到該現象的影響下,快閃記憶體內的資料只能在有限的時間內安全地儲存,隨著資料的保留時間增加,保留錯誤率也會逐漸增加,一旦保留錯誤率超出ECC的校正能力,資料的可靠性就會受到顯著的影響,由於保留錯誤是快閃記憶體的主要錯誤,而不同的狀態具有不同的保留錯誤率,因此本文提出了一種新型編碼方法,藉由減少高錯誤率狀態的數量以改善快閃記憶體的可靠度,根據實驗結果,比起先前相關研究我們可以更有效地降低保留錯誤率,以提高快閃記憶體的可靠性。


    Because NAND flash memory has limited P/E cycles, serious reliability problems will occur after P/E cycles that exceed the limit of flash memory units. The main reason is that the wear-out phenomenon in the flash memory cell. Under the influence of this phenomenon, the data in the flash memory can only be safely stored for a limited time (i.e., the retention time). As the retention time of the data increases, the retention error rate will gradually increase. Once the retention error rate exceeds the correction capability of ECC, the data Reliability will be significantly affected. Because retention errors are the main errors of flash memory, and different states have different retention error rates. In the thesis, we propose a new encoding method that reduces the high error rate state to improve the reliability of the flash memory. According to the experimental results, we can reduce the retention error rate more effectively than previous related works to improve the reliability of the flash memory.

    第一章 緒論 1.1 前言 1.2 論文架構 第二章 環境背景 2.1 NAND Flash Memory 2.3 SLC、MLC、TLC架構 2.4 Architecture Restriction 2.6 ECC 2.7 Data Retention Errors 2.8 Bit Flip and Permutation Strategy 2.9 Refresh Mechanisms 2.10 Bad Block Management 第三章 研究動機與相關研究 3.1 研究動機 3.2 相關研究 第四章 基於TLC快閃記憶體之保留錯誤緩解的位元配對寫入方法 4.1 概述 4.2 Processing Units (PUs) 4.3 PU排列表 4.4 開銷分析 4.5 案例探討 第五章 實驗與效能分析 5.1 實驗環境與工作負載 5.2 實驗結果 第六章 結論 第七章 參考文獻

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