使用六階RLC共振腔之三頻帶除三注入鎖定除頻器與除二注入鎖定除頻器之設計

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研究生：	鄭惟中 Wei-Chung Cheng
論文名稱：	使用六階RLC共振腔之三頻帶除三注入鎖定除頻器與除二注入鎖定除頻器之設計 Design of Triple-band Divide-by-3 and Divide-by-2 Injection-Locked Frequency Divider Using 6th-Order RLC Resonator
指導教授：	張勝良 Sheng-Lyang Jang 徐敬文 Ching-Wen Hsue
口試委員:	黃進芳 Jhin-Fang Huang 馮武雄 Wu-Shiung Feng
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2015
畢業學年度：	103
語文別：	英文
論文頁數：	133
中文關鍵詞：	注入鎖定除頻器、除二、除三
外文關鍵詞：	ILFD, Divide-by-2, Divide-by-3
相關次數：	點閱：246 下載：0
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首先，本論文提出一個三頻帶注入鎖定除三除頻器被實現在台積電點一八製程。此電路是以交叉耦合的壓控振盪器作為基礎，並加上六階RLC共振腔來實現。此電路在可調電壓下，可以產生三個振盪頻帶與三個鎖頻範圍。在直流汲極源極偏壓在0.9伏特，注入訊號強度為0dBm時，可得三個注入鎖定頻帶分別為8.51~11.98 GHz， 4.92~8.64 GHz 與 4.88~5.93 GHz。我們可以找到一個寬鎖定範圍為4.38~8.82 GHz。此晶片的核心功率消耗為6.759 mW，晶片面積為0.991×1.045 mm2。

其次，我們將相同的除三除頻器使用單端注入訊號。經由控制可變電容對間的電壓，相同地可以產生三個振盪頻帶與三個鎖頻範圍。當注入訊號為0 dBm時，在高、中、低頻的鎖頻範圍分別為8.41~11.46 GHz， 5.40~8.68 GHz 與 4.78~5.77 GHz.。
最後，一個寬鎖定範圍注入鎖定除二除頻器被實現在台積電點一八製程。此電路是以交叉耦合的壓控振盪器作為基礎，並加上六階RLC共振腔來實現。在直流汲極源極偏壓在0.9伏特，注入訊號強度為0dBm時，可得到最大鎖定範圍5.77GHz，經可變電容對間的開關操作，可得全電路的操作頻帶為2.05~8.76 GHz。此晶片的核心功率消耗為6.76 mW。

First, a triple-band divide-by-3 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-3 ILFD use a cross-coupled nMOS pair and a 6th order RLC resonator with three resonant frequencies. The ILFD has three oscillation frequency bands and three locking ranges, which can be measured at fixed tuning bias and tuning bias. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the high-band, middle-band and low-band locking range of the divide-by-3 ILFD are, respectively, 3.47GHz (33.87％) from 8.51 to 11.98 GHz, 3.72GHz (54.86％) from 4.92 to 8.64 GHz and 1.05GHz (19.76％) from 4.88 to 5.93 GHz. The largest locking range is given by 4.43GHz (67.07%) from 4.39 to 8.82 GHz. The core power consumption is 6.759 mW. The die area is 0.991×1.045 mm2.

Secondly, the divide-by-3 ILFD uses a single-ended injection signal, a cross-coupled nMOS pair and an injection MOSFET. The divide-by-3 ILFD has three oscillation frequency bands and three locking ranges via varactor control voltage. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the high-band, middle-band and low-band locking range of the divide-by-3 ILFD are, respectively, given by 3.05GHz (30.70％) from 8.41 to 11.46 GHz, 3.28GHz (46.59％) from 5.40 to 8.68 GHz and 0.99GHz (18.77％) from 4.78 to 5.77 GHz. The operation range is 6.68GHz, extending from 4.78 to 11.46 GHz.

Finally, a wide-band divide-by-2 LC injection-locked frequency divider was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD uses a cross-coupled nMOS pair and a 6th order RLC resonator. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm, the maximum locking range of the divide-by-2 ILFD is 5.77GHz (105.2％) from 2.6 to 8.37 GHz, and the operation range is 6.71GHz (124.14％) from 2.05 to 8.76 GHz via varactor switching. The core power consumption is 6.76 mW.

中文摘要	I
Abstract	III
致謝	V
Table of Contents 	VI
List of Figures 	IX
List of Tables 	XVII
Chapter 1 Introduction 	1
1 Background 	1
2 Thesis Organization 	4
Chapter 2 Overview of the Voltage–Controlled Oscillators 	5
1 Introduction 	6
2 Design Parameters of Voltage Controlled Oscillator 	7
3 Basic Theory of Oscillators 	 11
3.1 One-Port (Negative Resistance) View	12
3.2 Two-Port (Feedback) View 	15
4 Oscillators 	17
4.1 Ring Oscillator 	18
4.2 LC-Tank Oscillator 	22
4.3 Research in RLC Tank 	26
4.4 Type of the LC Oscillator 	29
4.4.1  Single Transistor Oscillator 	31
4.4.2  One-Port Oscillator (Negative-Gm Oscillator) 	33
4.4.3  Cross-Coupled Oscillator 	37
4.4.4  Complementary Cross-Coupled Topology 	39
5 Quality Factor 	42
6 Phase Noise 	43
6.1 Definition of Phase Noise	43
6.2 Linear Time-Invariant  (LTI) Phase Noise Model 	44
6.3 Linear Time-Variant Phase Noise Model 	48
6.4 Classification of Noise 	51
6.4.1  Thermal noise 	51
6.4.2  Flicker noise 	53
6.5 Phase Noise in Communications 	54
6.6 Models of Phase Noise 	56
6.7 Figure of Merit 	56
7 Elements of Semiconductor Process 	57
7.1 Resistor 	57
7.2 Inductor 	58
7.3 Transformer 	66
7.3.1  Planar transformer  	68
7.3.2  Stacked transformer 	69
7.4 Capacitor 	71
7.5 Varactor 	73
7.5.1  P-N Reverse Biased Diode  	73
7.5.2  MOS Varactor 	75
7.5.3  The Accumulation-Mode (A-mode) MOS Capacitor 	77
7.5.4  The Inversion-Mode (I-mode) MOS Capacitor 	78
8 Dual-Band Resonator 	79
Chapter 3 Concepts and Design of Injection-Locked Frequency Divider 	83
1 Principle of Injection-Locked Frequency Divider 	84
2 Locking Range 	86
3 Direct ILFD 	88
Chapter 4 A Triple-band Divide-by-3 Injection-Locked Frequency Divider Using
                  6th-Order RLC Resonator 	90
1 Introduction 	90
2 Circuit Design 	91
3 Measurement Result 	95
Chapter 5 Divide-by-3 Injection-Locked Frequency Divider with Multi-
                  Resonator  	101
1 Introduction 	101
2 Circuit Design 	103
3 Measurement Result 	110
Chapter 6 A Wide-band Divide-by-2 Injection-Locked Frequency Divider Using
                  6th-Order Resonator 	116
1 Introduction 	116
2 Circuit Design 	117
3 Measurement Result 	121
Chapter 7 Conclusion 	125
References 	127

                                

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全文公開日期 2020/08/03 (校內網路)
全文公開日期本全文未授權公開 (校外網路)
全文公開日期本全文未授權公開 (國家圖書館：臺灣博碩士論文系統)

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