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研究生： 莊政威
Jheng-Wei Jhuang
論文名稱： 新式互補金氧半雙共振注入鎖定倍頻器與除頻器設計
New Type CMOS Dual Resonances Injection Lock Doubler and Divider Design
指導教授： 張勝良
Sheng-Lyang Jang
徐敬文
Ching-Wen Hsue
口試委員: 黃進芳
Jhin-Fang Huang
馮武雄
W. S. Feng
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 英文
論文頁數： 125
中文關鍵詞： 注入鎖定除頻器 、注入鎖定倍頻器 、壓控振盪器
外文關鍵詞： injection-locked frequency divider, injection-locked frequency doubler, voltage-controlled oscillator
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    • 在RF收發機機裡，其中在重要的鎖相迴路裡（PLL）有電壓控制振盪器（VCO）、除頻器與倍頻器電路， PLL消耗功率最大的是振盪器和除頻器，除頻器與倍頻器需求的較寬鎖定頻率範圍、低消耗功率、低相位雜訊，防止由除頻器電路關閉干擾而破壞混頻器轉換的信號，並由優化指數定義其特性的好壞。
    首先提出在0.18 um MOSFET和一個雙共振的RLC諧振器的交叉耦合振互補式金屬氧化物半導體製程的雙共振的CMOS LC儲能注入鎖定倍頻器（ILFM），並描述了ILFM的電路設計、操作原理以及測量結果，鎖定倍頻器電路由RLC雙共振一次諧波注入鎖定振盪器（ILO），用雙注入的方式饋入，讓寬頻帶倍頻使用電阻來降低諧振的品質因數並且增強了鎖定範圍，在1.65 V的電源電壓，直流功耗為7.71 mW，與0 dBm的入射功率時，儲能注入鎖定倍頻器具有從3.9 GHz至8.2 GHz的鎖頻範圍。
    其次，用雙共振RLC具有低和高注入功率寬鎖定範圍注入鎖定除頻器（ILFD），用0.18 um 1P6M互補式金屬氧化物半導體注入鎖定除頻器基於與直接注入盪器，電阻器被用來增強鎖定範圍，在0.85 V的汲源極偏壓，並且在0 dBm的除以2 ILFD的鎖定範圍的入射功率為7.14 GHz，注入頻率從3.18到10.32 GHz，鎖定範圍百分比大約105.8 ％， ILFD核心的功率消耗為6.59 mW。該面積為0.785×0.883 mm2。
    第三，設計了寬鎖定範圍除4 LC注入鎖定分頻器（ILFD），用0.18μm 1P6M CMOS ILFD基於直接注入MOSFET和一個RLC諧振器的交叉耦合振盪器，電阻用於增強鎖頻範圍，在0.9 V的汲極源極偏壓，並且在0 dBm的除4 ILFD的鎖定範圍的注入功率為4.508 GHz，注入頻率從11.92至16.428 GHz時，鎖定範圍百分比為32.11 ％。 ILFD的功率消耗為9.68 mW。
    最後，用除2雙共振RLC注入鎖定除頻器（ILFD）被設計為ILFD電路工作原理射頻特性研究。用該0.18 um 1P6M CMOS ILFD基於與直接注入MOSFET和一個雙共振的RLC諧振器的交叉耦合振盪器。在1 V的極源極偏壓，並且在0 dBm的除2 ILFD的鎖定範圍的輸入頻率為7.16 GHz，注入頻率從3.6 GHz到10.72 GHz，鎖頻範圍百分比為99.5 ％。 注入鎖定除頻器功率消耗為12.18 mW。晶片面積為1.052×0.849 mm2。電阻是被用來增強鎖定範圍。基頻ILFD振盪調整顯示遲滯。

    In the RF transceiver, the important blocks in the phase locked loop (PLL) are the voltage control oscillator (VCO) and the divider and doubler circuit. The most power consumption of PLL consumes in VCO and divider. The divider is requested the wide locking range, low power, and the low phase-noise to prevent corrupting the mixer-converted signal by close interfering tones for divider circuit, and the Figure of Merit (FOM) of divider and doubler can be determined by it is performance.
    First, this proposes a dual-resonance CMOS LC-tank injection locked frequency doubler (ILFM) fabricated in the 0.18 μm CMOS process and describes the circuit design, operation principle and measurement results of the ILFM. The ILFM circuit is composed of a RLC dual-resonance first-harmonic injection-locked oscillator (ILO), a wide-band frequency doubler with differential-injection ports. The ILFM uses resistors to degrade the resonator quality factor and enhance the locking range. At the supply voltage of 1.65 V, the dc power consumption is 7.71 mW. At the incident power of 0 dBm, the ILFM has locking range from the incident frequency 3.9 GHz to 8.2 GHz.
    Secondly, this designs a divide-by-2RLC injection-locked frequency divider (ILFD) having wide locking range at both low and high injection power. The 0.18μm 1P6M CMOS ILFD is based on a cross-coupled oscillator with a direct injection MOSFET and a dual-resonance RLC resonator. The resistor is used to enhance the locking range. At the drain-source bias of 0.85 V, and at the incident power of 0 dBm the locking range of the divide-by-2 ILFD is 7.14 GHz, from the incident frequency 3.18 to 10.32 GHz, the locking range percentage is 105.8%. The power consumption of ILFD core is 6.59 mW. The die area is 0.785× 0.883 mm2.
    Third, this thesis designs a wide locking range divide-by-4 LC injection-locked frequency divider (ILFD). The 0.18 μm 1P6M CMOS ILFD is based on a cross-coupled oscillator with a direct injection MOSFET and a RLC resonator. Resistors are used to enhance the locking range. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the locking range of the divide-by-4 ILFD is 4.508 GHz, from the incident frequency 11.92 to 16.428 GHz, the locking range percentage is 32.11%. The power consumption of ILFD core is 9.68 mW.
    Finally, a divide-by-2 dual-resonance RLC injection-locked frequency divider (ILFD) has been designed for the study of RF property of ILFD circuit operation principle. The 0.18 μm 1P6M CMOS ILFD is based on a cross-coupled oscillator with a direct injection MOSFET and a dual-resonance RLC resonator. At the drain-source bias of 1 V, and at the incident power of 0 dBm the locking range of the divide-by-2 ILFD is 7.16 GHz, from the incident frequency 3.6 to 10.72 GHz, the locking range percentage is 99.5 %. The power consumption of ILFD core is 12.18 mW. The die area is 1.052×0.849 mm2. The resistor is used to enhance the locking range. The free-running ILFD oscillation tuning shows hysteresis.

    Table of Contents Chapter 1 Introduction 1 1.1 Background 1 1.1.1 Low Noise Amplifier 2 1.1.2 Mixer 3 1.1.3 A/D Converter and D/A Converter 3 1.1.4 Power Amplifier 4 1.15 Local Oscillator 4 1.2 Motivation Research 5 Chapter 2 The Overview of Oscillators 7 2.1 Basic Theory of Oscillators 7 2.1.1 The Oscillator Principle 9 2.1.2 Introduced Voltage Control Oscillator Species 12 2.2 Basic Theory of Frequency Divider and Doubler 12 2.2.1 The Frequency Divider Principle 12 2.2.2 The Frequency Doubler Principle 15 2.3 The Parameters of Voltage Control Oscillator, Frequency Divider and Doubler 16 2.3.1 Power Dissipation [mW] 16 2.3.2 Quality Factor 16 2.3.3 Output Signal Purity 21 2.3.4 Tuning Sensitivity [Hz/V] 21 2.3.5 Phase Noise [dBc/Hz] 22 2.3.6 Injection Locking [GHz] 24 2.3.7 FOM for Voltage Control Oscillator (FoM) [dBc/Hz] 25 2.3.8 FOM for Frequency Divider and Doubler [dBc/Hz] 26 Chapter 3 Wide-Band Injection-Locked Frequency Doubler 27 3.1 Introduction 27 3.2 Circuit Design 28 3.3 Measurement and Discussion 30 3.4 Summary 38 Chapter 4 Divide-by-2 Injection-Locked Frequency Divider Using Dual-Resonance RLC Resonator 39 4.1 Introduction 39 4.2 Circuit Design 40 4.3 Measurement and Discussion 42 4.4 Summary 61 Chapter 5 Divide-by-4 Injection-Locked Frequency Divider with Resistive Enhancement Technique 62 5.1 Introduction 62 5.2 Circuit Design 63 5.3 Measurement and Discussion 66 5.4 Summary 80 Chapter 6 Study on Divide-by-2 Injection-Locked Frequency Divider Using Dual-Resonance RLC Resonator 81 6.1 Introduction 82 6.2 Circuit Design 82 6.3 Simulation Study 83 6.4 Measurement Results and Discussion 87 6.5 Summary 99 Chapter 7 Conclusion 100 References 102

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