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| 研究生： |
潘麒安 Chi-An Pan |
|---|---|
| 論文名稱： |
基於整數線性規劃之細間距球柵陣列封裝基板繞線架構 Integer Linear Programming Based Substrate Routing Framework for Fine Pitch Ball Grid Array Package |
| 指導教授： |
劉一宇
Yi-Yu Liu |
| 口試委員: |
吳坤熹
Kun-Hsi Wu 方劭云 Shao-Yun Fang 謝仁偉 Jen-Wei Hsieh 陳勇志 Yung-Chih Chen |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 資訊工程系 Department of Computer Science and Information Engineering |
| 論文出版年： | 2019 |
| 畢業學年度： | 107 |
| 語文別： | 英文 |
| 論文頁數： | 43 |
| 中文關鍵詞： | 封裝 、細間距球柵陣列 、基板繞線 、整數線性規劃 |
| 外文關鍵詞： | Packaging, FBGA, Substrate Routing, ILP |
| 相關次數： | 點閱：357 下載：1 |
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在先進的超大型積體電路設計中，一個晶圓上可能會有上億個電晶體，因此積體電路封裝在晶片設計流程中越趨重要。細間距球柵陣列被廣泛的應用於空間非常限制之應用，例如行動裝置、手持裝置等等。為了解決複雜的設計規則，基板連接通常由有經驗之工程師手動完成，但是基板連接非常複雜，因此手動完成是非常耗時以及經常出錯的。我們提出基於整數線性規劃的自動繞線器來加速工程師完成基板繞線，並且同時考慮複雜的設計限制以及不協調的鑽孔大小。更進一步提出三個減少整數線性規劃中限制的方法來加速時間，實驗結果顯示我們提出來之架構可以有效的降低基板連接的設計時間。
In advanced very-large-scale integration (VLSI) design, billions of transistors could be fabricated on the same die.
Integration circuit (IC) packaging has become one of the most important steps in IC design flow.
Fine pitch ball grid array (FBGA) is widely used in space constrained applications, such as mobile and handheld devices.
These packaging substrate interconnections are usually customized by layout engineers taking many complex and stringent design rules into considerations.
However, fully net-by-net manual design for FBGA is time consuming and error-prone.
In this thesis, we propose an integer linear programming (ILP) based router for wire-bonding FBGA packaging design.
Our ILP formulation takes design-dependent constraints and mismatched via dimension into account.
Three ILP constraint reduction techniques are developed to boost the run time of ILP optimization.
Experimental results indicate that our framework could effectively reduce the substrate layout design cycle time.
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[12] J. S. Wu, ''Optimization strategies for integer linear programming based ball grid array substrate router,'' M. S. thesis, National Taiwan University of Science and Technology, Taipei, Taiwan, 2019.
