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研究生: 沈伯賸
Po-Sheng Shen
論文名稱: 搭配原子層沉積之高介電係數雙閘極絕緣層改善低操作 電壓氧化銦鋅錫薄膜電晶體電特性及可靠度
Improvement of Performance and Stability for Low Operating Voltage InZnSnO Thin-Film Transistors with High-k Bilayer Gate Insulator Layers by Atomic Layer Deposition
指導教授: 范慶麟
Ching-Lin Fan
口試委員: 范慶麟
李志堅
劉舜維
顏文正
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 中文
論文頁數: 172
中文關鍵詞: 氧化銦鋅錫薄膜電晶體原子層沉積鈍化層高介電係數
外文關鍵詞: amorphous indium–zinc–tin-oxide, thin-film transistor, atomic layer deposition, passivation layer, high-k
相關次數: 點閱:231下載:0
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由於金屬氧化物薄膜電晶體的製程特質及材料特性,使它們在新興的薄膜電晶體應用上成為最具有競爭性的選擇,包含均勻性好可以應用在大尺寸的面板、可在低溫下製作而應用於可撓式的裝置以及低成本製作等特殊需求的產品上。為了滿足下一世代的顯示器,薄膜電晶體的載子遷移率需要更高,所以本論文將搭配高介電係數材料二氧化鉿及氧化鋁來製備元件之閘極絕緣層,並使用氧化銦鋅錫來當作主動層,因為氧化銦鋅錫具有比氧化銦鎵鋅更高的載子遷移率,但是氧化銦鋅錫其材料特性較不穩定,所以本論文將透過更換閘極電極及製作鈍化層來提升元件穩定性。
首先,我們利用磁控濺鍍以及原子層沉積製作氧化銦鋅錫薄膜電晶體之閘極絕緣層,分析不同閘極絕緣層的製程方式、薄膜厚度以及材料比例對於元件的影響,並找出一個最佳的參數。之後,為了提升元件的穩定度,我們將閘極換成了穩定度較高的氮化鉭,並且以原子層沉積製作了以多層堆疊二氧化鉿及氧化鋁形成之鈍化層。在本實驗中發現,原子層沉積之氧化鋁具有較少的介面缺陷,在遲滯特性方面有大幅度的改善。而具有圖案化的氮化鉭閘極有效的降低了元件的漏電流,有效的提升了元件的製程良率。在鈍化層方面,因為薄膜品質較為緻密能有效阻擋水氣及氧氧侵蝕主動層,大幅地提高了元件的穩定度。


Amorphous oxide semiconductor (AOS) materials are considered to be the most competitive thin film transistor (TFT) material for last decade. They have several advantages such as great uniformity for large size display, low fabrication temperature and low production cost. For next generation display, the TFT devices need being improved, especially in mobility. In order to get higher on /off current ratio on AOS-TFT, high-k dielectric was used as the gate insulator in TFT structure. And then in order to pursue greater AOS TFT performance, indium zinc tin oxide (IZTO) was introduced as the active layer, because IZTO-TFT has higher mobility than IGZO-TFT. However, the material properties of IZTO are relatively unstable, so this work will displace indium tin oxide (ITO) to tantalum mononitride (TaN) and manufacture passivation layer to improve stability of IZTO TFT.
First, we fabricated gate insulator of IZTO-TFT with RF magnetron sputter deposition and atomic layer deposition (ALD), analyzed the influence of different gate insulator layer process methods, thickness and the ratio of hafnium oxide (HfO2) and aluminum oxide (Al2O3) and try to find a best condition. Afterwards, in order to improve the stability of the device, we decide to change the gate electrode. Since TaN has higher stability, we replace the indium tin oxide (ITO) with TaN. Then, we fabricated a passivation layer formed by stacking HfO2 and Al2O3 by atomic layer deposition. In this experiment, we found that the Al2O3 deposited by ALD has fewer interface traps and has a significant improvement in hysteresis characteristics. The patterned TaN as gate electrode effectively reduces the leakage current of the device and improves the process yield of the device. In the passivation layer, due to better film quality can effectively block the corrosion of water vapor and oxygen and improve the stability of device.

論文摘要 I Abstract II 誌謝 IV 目錄 V 圖目錄 IX 表目錄 XVI 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機 5 1.3 論文大綱 6 第二章 材料與製程介紹及參數萃取 8 2.1 閘極絕緣層高介電材料 8 2.1.1 元件尺寸的發展 8 2.1.2 高介電材料的興起 9 2.1.3 高介電材料的選擇 11 2.1.4 常見的高介電材料的種類 14 2.1.5 高介電材料之製程方式 14 2.2 金屬氧化物半導體材料介紹 15 2.2.1 金屬氧化物半導體材料概述 15 2.2.2 非晶金屬氧化物半導體傳輸機制 16 2.2.3 非晶氧化銦鋅錫材料特性與電性影響 19 2.3 金屬氧化物薄膜電晶體結構 23 2.4 金屬氧化物薄膜電晶體操作 25 2.5 金屬氧化物薄膜電晶體之重要參數萃取 30 2.5.1 載子遷移率(Mobility, μ) 30 2.5.2 臨界電壓 (Threshold Voltage, VTH) 32 2.5.3 次臨界斜率 (Subthreshold Swing, S.S) 33 2.5.4 開關電流比(On/Off Current Ratio, IOn/IOff) 34 2.5.5 接觸電阻(Contact Resistance, RC) 35 2.5.6 電容I-V特性量測 36 2.5.7 C-V電特性量測 36 2.5.8 半導體參數分析儀 (Semiconductor Parameter Analyzer) 37 2.6 薄膜材料特性分析 38 2.6.1 場發射掃描式電子顯微鏡 (Field Emission Scanning Electron Microscope, FESEM) 38 2.6.2 能量色散X射線譜(Energy-Dispersive X-ray Spectroscopy, EDS) 38 2.6.3 電容電感電阻量測儀 (LCR Meter) 39 2.6.4 原子力顯微鏡 (Atomic Force Microscope , AFM) 39 2.6.5 紫外光/可見光光譜儀(Ultraviolet/Visible Spectrophotometer, UV/VIS) 40 2.6.6 薄膜厚度輪廓測量儀(Alpha-Step, α-step) 43 2.6.7 二次離子質譜儀分析(Second Ion Mass Spectroscopy, SIMS) 43 2.6.8 水氣滲透率量測儀(Water Vapor Transmission Rate, WVTR) 44 2.6.9 X 射線光電子能譜儀( X-ray Photoelectron Spectroscopy, XPS) 45 2.7 金屬氧化物薄膜電晶體之製程介紹 47 2.7.1 濺鍍法(Sputter) 47 2.7.2 原子層沉積法(Atomic Layer Deposition, ALD) 47 2.7.3 熱蒸鍍法(Thermal Evaporation Deposition) 47 第三章 原子層沉積之閘極絕緣層改善電特性之研究 48 3.1 原子層沉積介紹 48 3.2 實驗說明 52 3.3 實驗步驟 53 3.4 不同參數之閘極絕緣層之元件實驗分析 62 3.4.1 不同製程之閘極絕緣層電容量測分析 62 3.4.2 使用不同製程閘極絕緣層之薄膜電晶體電特性分析 64 3.4.3 使用不同製程閘極絕緣層之薄膜電晶體遲滯特性分析 68 3.5 不同閘極絕緣層之元件實驗分析 71 3.5.1 不同閘極絕緣層之元件電特性分析 71 3.5.2 使用不同閘極絕緣層之薄膜電晶體遲滯特性分析 74 3.6 不同厚度閘之極絕緣層元件實驗分析 76 3.6.1 不同厚度之閘極絕緣層元件電特性分析 76 3.6.2 不同厚度之閘極絕緣層元件遲滯特性分析 81 3.7 相同厚度不同製程之閘極絕緣層元件實驗分析 85 3.7.1 相同厚度不同製程之閘極絕緣層元件電特性分析 85 3.7.2 相同厚度不同製程之閘極絕緣層元件遲滯特性分析 90 3.8 不同比例之閘極絕緣層元件實驗分析 92 3.8.1 不同比例之閘極絕緣層元件電特性分析 92 3.8.2 不同比例之閘極絕緣層元件遲滯特性分析 95 第四章 探討氮化鉭閘極與製作鈍化層對於穩定度之影響 97 4.1 簡介 97 4.2 實驗說明 102 4.3 實驗步驟 102 4.4 不同閘極元件之實驗分析 107 4.4.1 不同閘極元件電特性分析 107 4.4.2 不同閘極元件遲滯特性分析 112 4.5 降低操作電壓 114 4.6 HfO2/Al2O3堆疊鈍化層實驗分析 119 4.6.1 實驗步驟 119 4.6.2 有無鈍化層之元件穩定度分析 122 4.6.3 在正閘極偏壓(Positive Gate Bias Stress, PGBS)劣化下元件可靠度之研究 122 4.6.4 在負閘極偏壓(Negative Gate Bias Stress, NGBS)劣化下元件可靠度之研究 128 4.6.5 具有鈍化層之元件於大氣下水氧劣化測試 134 第五章 結論與未來展望 136 5.1 結論 136 5.2 未來展望 138 參考文獻 140

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