本論文提出一個實現於現場可程式化閘陣列(Field Programmable Gate Array，FPGA)並利用鎖相迴路延遲矩陣為基礎之時間至數位轉換電路(Time-to-Digital converter，TDC)。由於過往以二維游標法為基礎之FPGA TDC [1]無法讓所有延遲級的延遲時間完全受到控制，故其性能受到延遲時間隨機分佈的強烈影響，進而增添電路設計上之複雜度。再者，此架構的限制也令其僅能量測20ns範圍以內的輸入時間寬度訊號，大大降低電路之實用性。有鑒於此，本論文改採PLL構建二維延遲矩陣的方式，俾實現一個高準確度、以二維游標法為基礎的FPGA TDC。
本論文透過FPGA内建之鎖相迴路來構建一個PLL 串接型態之二維延遲矩陣，藉由主PLL與次PLL提供恆定且不受PVT變異影響之多個不同的時脈相位，讓所有時脈之相位均勻分佈在0~360度之參考週期內，並搭配雙倍資料率的分相概念，在相同的延遲矩陣架構下創造兩倍的有效相位數，以大舉提高有效的時間解析度，進而達到15.6ps且不受PVT變異影響的解析度。另外也採用大數法則將複數組計數器矩陣的結果加總平均來實現低單擊精密度與低非線性誤差，最後再加入偏移校準技術更進一步降低PVT變異對偏移量的影響，並將輸出偏移誤差抑制在0.3個LSB之內。長線量測之積分非線性誤差(INL)為-0.145 ~ 0.155 LSB、差分非線性誤差(DNL)為-0.212 ~ 0.182 LSB。並完整測試涵蓋0C到50C的運作功能，成功驗證本時間至數位轉換電路抑制溫度變異之優異效果，整體效能甚至優於大部分的全客戶(Full Custom)設計競爭對手。

Conventionally, a 2-D Vernier FPGA TDC was able to achieve 2.5 ps bin size and -2.98~ 3.23 LSB integral nonlinearity (INL) [1]. However, the cell delays of the delay lines cannot be fully controlled. Thus, the TDC performance is strongly dependent on the stochastic distribution of the cell delays. Moreover, the input range is limited to be less than 20ns. A flexible PLL delay matrix capable of double data rate (DDR) operation is proposed in this thesis to generate uniform reference clock phase divisions over [0-2] with much immunity to PVT variations for high accuracy time-to-digital converter implementation.
The proposed TDC is aimed to provide a PVT-insensitive solution with both high resolution and wide measurement range. The delay of all cells is under the precise control of major and minor PLLs. With the newly proposed phase division scheme, the PLL output phases are distributed uniformly within the reference period to achieve an extremely fine resolution. The double data rate (DDR) operational principle is incorporated to further enhance the realizable resolution. Finally, averaging is adopted to improve the measurement accuracy.
To demonstrate the feasibility and performance of the DDR PLL matrix, a FPGA TDC is realized accordingly to achieve 15.6 ps resolution. To reduce the impact of temperature-sensitive offset, a cancellation circuit is adopted to substantially reduce the offset and confine the output difference to within merely 0.3 LSB. The measured differential and integral non-linearities are -0.212 ~ 0.182 LSB and -0.145 ~ 0.155 LSB respectively to prove the superiority of the proposed structure. This TDC was tested to be fully functional over 0C to 50C ambient temperature range with very low resolution variation. Its performance is even superior to many full-custom TDC designs.

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