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研究生： 盧克樺
Kei–Hua - Lu
論文名稱： 運用展頻技巧降低參考突波的1.8伏特2.4 GHz整數型鎖相迴路晶片設計
A 2.4 GHz Phase Locked Loop with Spur Reduction Using Frequency Expansion Technique
指導教授： 張勝良
Sheng–Lyang Jang
口試委員: 黃進芳
Jhin-Fang Huang
徐敬文
Ching-Wen Hsue　
賴文政
Wen Cheng Lai
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 英文
論文頁數： 105
中文關鍵詞： 鎖相迴路 、突波消除 、頻率延展
外文關鍵詞： Phae-Locked-Loop, Spur Reduction, Frequency Expansion
相關次數： 點閱：248  下載：4 
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    • 近年來，隨著無線通訊系統快速發展，各種的頻率合成器被研發出來，又以單晶片系統(System-on-Chip)為主要趨勢，在整合各系統子電路時常出現操作時脈相位不同的情況，而導致輸出資料錯誤，因此需要鎖相迴路(Phase-locked-Loop, PLL)來減少相位偏差，使得整合系統中各個子電路的時脈相位一致，減少輸出誤差。其中壓控震盪器(VCO)為關鍵核心電路。其中壓控震盪器(VCO)為關鍵核心電路，原因在於PLL藉著輸入的電壓去調整頻率的快慢產生穩定的波形，最後達到鎖定的功能，因此VCO的好壞會大大影響PLL的性能，所以在VCO電路的設計上，必須要注意相位雜訊(phase noise)、調整範圍(tuning range)等重要效能參數。
    第一顆晶片，我們介紹了一個降低參考突波技巧的2.4 GHz整數型鎖相迴路的架構。使用了以注入脈衝方式為主的頻率擴展方式，主要功用為讓內部的脈衝頻率擴展，並抑制參考頻率處的突波，其能達到低突波與低相位雜訊的性能。此頻率合成器是使用台積電所提供0.18微米CMOS製程以1.8伏特來完成晶片研製與量測，而量測結果顯示頻率範圍為2.25~2.45 GHz，其8.5%，頻率鎖定在2.3 GHz時，距離主頻1 MHz處的相位雜訊為-113.2 dBc/Hz，參考訊號突波高度為-44 dBc，功率消耗為24.2 mW，晶片面積含Pad後為0.712 mm2。
    第二顆晶片，我們設計了一個由兩組壓控震盪器所組成的四相位壓控震盪器並採用了Class-C電路提高了擺幅，讓整體進入穩態的功率降低，也降低了相位雜訊。此四相位壓控震盪器是使用台積電所提供0.18微米CMOS製程以1伏特來完成晶片研製與量測，而量測結果顯示頻率範圍為2.58~3.25 GHz，其23%，質量因數(FoM)為-190.5dB，考慮調頻範圍的質量因數(FoMT)為-197dB，功率消耗為4.6 mW，晶片面積含Pad後為0.712 mm2。
    第三顆晶片，我們設計了一個由多個電感所組成的寬除頻範圍的注入式鎖定除頻器。與一般常規的諧波混波器的注入式除頻器不同，在諧震器裡面加入了電阻來增加除頻範圍。此注入式鎖定除頻器是使用台積電所提供0.18微米CMOS製程以0.9伏特來完成晶片研製與量測，而量測結果顯示除頻範圍為9.2~12.5 GHz，其30.6%，質量因數(FoM)為11.3dB，功率消耗為2.7 mW，晶片面積含Pad後為0.987x1.096mm2。

    In recent year, with the rapid growing of the wireless communication system, many of PLL architectures are created. The chip changes to integrate SOC. There is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. The different phase of operate clock that caused to output data error in integrate system. Hence, it needs Phase-Locked Loop (PLL) for decreasing phase error that make the clock phase is corresponding in order to decrease output data error in sub-circuit of integrate system. Among the VCO is the most important circuit in the PLL. The reason is that the PLL needs to produce stable waveform to control frequency by adjust control voltage. Finally achieve the lock function. Therefore the quality of VCO will affect the performance of the PLL. When we design the VCO, we need to notice the important efficacy parameters especially.
    The first chip, we design a 2.4GHz PLL using a spur reduction technique with the frequency expansion. The architecture using frequency expansion is shown in Fig. 2. It can achieve spur suppression by using pulse-interpolator and lock detector (LD) in the architecture. The proposed phase-locked-loop operates with 1.8 V supply voltage is fabricated in TSMC 0.18-µm CMOS process. Measured results shows a wide tuning range from 2.25 GHz to 2.45 GHz, a phase noise of -113.2 dBc/Hz at 1 MHz offset from 2.4 GHz, a reference spur of -44 dBc, a power consumption of 24.2 mW and the with pads chip area is only 0.712 mm2.
    The second chip, we adopt a class C quadrature voltage-controlled oscillator (QVCO) based on capacitor coupling in TSMC 0.18um CMOS 1P6M process technology. Comparing to conventional parallel-coupled QVCO, the proposed QVCO achieves a better phase noise and tuning range. The proposed QVCO operates from 2.58GHz to 3.25GHz(23%). The measured phase noise at 1MHz offset frequency is -128.8 dBc/Hz and the measured phase error of quadrature signals are 0.45。 At 2.58GHz. With 1V power supply, the power consumption is 4mW. The figure of merit (FOM) of proposed QVCO is -190.5 dBc/Hz, FOMT = -197 dBc/Hz. The die area is 1197um × 595um.
    The second chip, we proposes a new wide-locking range ÷5 ILFD with capacitive cross-coupled oscillator; resistors are used in the resonator to degrade the quality factor so that locking range is enhanced. At the incident power of 0 dBm the maximum locking range of the implemented divide-by-5 ILFD is 3.2GHz (30.6%) from 9.2 to 12.5 GHz. This is larger than other published divide-by-5 LC-ILFDs. The die area is 0.987um ×1.096um.

    List of Figures IV List of Tables IX Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Focus and Contributions 2 1.3 Organization of This Thesis 2 Chapter 2 The Basics of Frequency Synthesizers 4 2.1 Wireless Transceiver 4 2.2 Phase-Locked Loop 5 2.2.1 Integer-N Frequency Synthesizer 6 2.2.2 Fractional-N Frequency synthesizer 7 2.3 General Considerations 8 2.3.1 Phase Noise 8 2.3.2 Spurs 10 2.3.3 Jitter 11 2.4 Summary 12 Chapter 3 PLL Analysis and Circuit Design 13 3.1 Voltage-Controlled Oscillator Circuit (VCO) 13 3.1.1 General Operation Principles 14 3.1.2 Ring Oscillator Circuit 15 3.1.3 LC-Tank VCO Circuit 16 3.1.4 Switched-Capacitors VCO Circuit 19 3.2 Phase Frequency Detector Circuit (PFD) 21 3.3 Charge Pump Circuit (CP) 23 3.3.1 Single-Ended Charge Pump 24 3.3.2 Current-Steering Charge Pump 25 3.4 Frequency Divider 26 3.4.1 Pulse-Swallow Divider 26 3.4.2 Dual-Modulus Prescalers 27 3.4.3 Multi-Modulus Divider 28 3.4.4 Full-Modulus Divider 30 3.4.5 CML Divider and TSPC Divider 31 3.5 Loop Filter Design 32 3.6.1 First-Order Loop Filter 33 3.6.2 Second-Order Loop Filter 35 3.6.3 Third-Order Loop Filter 38 3.7 Summary 39 Chapter 4 A 2.4 GHz Phase Locked Loop with Spur Reduction Using Frequency Expansion Technique 40 4.1 Introduction 40 4.2 System Block Diagram 41 4.3 Building Block and Simulation 42 4.3.1 Voltage-Controlled Oscillator Circuit (VCO) 42 4.3.2 Frequency and Phase Detector Circuit (PFD) 46 4.3.3 Charge Pump Circuit (CP) 47 4.3.4 Programmable Divider Circuit 49 4.3.5 Lock Detector 55 4.3.6 Pulse-Interpolator 56 4.3.7 The Overall PLL System Simulation Results 57 4.4 Frequency Synthesizer Chip Measurements 58 4.4.1 Chip Floor Plan and PCB Design 58 4.4.2 Test Environment Setup 60 4.4.3 Measurement Results 61 4.5 Specifications and Performance Comparison 63 4.6 Summary 65 Chapter 5 A Low Phase Noise, Wide Tuning Range Quadrature VCO with Class C Technique 66 5.1 Introduction 66 5.2 Circuit Design 67 5.3 The Quadrature VCO Simulation Results 68 5.4 Frequency Synthesizer Chip Measurements 69 5.4.1 Chip Floor Plan and PCB Design 70 5.4.2 Test Environment Setup 71 5.4.3 Measurement Results 71 5.5 Specifications and Performance Comparison 73 5.6 Summary 74 Chapter 6 Wide-Locking Range Divide-by-5 Injection-Locked Frequency Divider 76 6.1 Introduction 76 6.2 Circuit Design 77 6.4 Divide-by-5 Injection-Locked Frequency Divider Measurements 79 6.4.1 Chip Floor Plan and PCB Design 83 6.5 Specifications and Performance Comparison 84 6.6 Summary 84 Chapter 7 Conclusions and Future Work 85 7.1 Conclusions 85 7.1.1 Chip1: A 2.4 GHz Phase Locked Loop with Spur Reduction Using Frequency Expansion Technique 85 7.1.2 Chip2: A Low Phase Noise, Wide Tuning Range Quadrature VCO with Class C Technique 85 7.1.3 Chip3: A Wide-Locking Range Divide-by-5 Injection-Locked Frequency Divider 86 7.2 Future Work 86 References 87

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